diff options
| author | Tom Warren <twarren@nvidia.com> | 2013-04-03 14:39:30 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2013-04-15 11:01:38 -0700 |
| commit | d94c2dbd0a55d742ab6ed9bd0c51b27ceed4084e (patch) | |
| tree | 5bdef44cb41f3818fec6d5741654bba1348ef19a /arch/arm/cpu/arm720t/tegra30/cpu.c | |
| parent | b40f734af9fdc47a0993f1f94f32d40a86f30587 (diff) | |
Tegra: Fix MSELECT clock divisors for T30/T114.
A comparison of registers between our internal NV U-Boot and
u-boot-tegra/next showed some discrepancies in the MSELECT
clock divisor programming. T20 doesn't have a MSELECT clk src reg.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/arm720t/tegra30/cpu.c')
| -rw-r--r-- | arch/arm/cpu/arm720t/tegra30/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c index dedcdd9b08..e162357484 100644 --- a/arch/arm/cpu/arm720t/tegra30/cpu.c +++ b/arch/arm/cpu/arm720t/tegra30/cpu.c @@ -110,8 +110,8 @@ void t30_init_clocks(void) reset_set_enable(PERIPH_ID_MSELECT, 1); clock_set_enable(PERIPH_ID_MSELECT, 1); - /* Switch MSELECT clock to PLLP (00) */ - clock_ll_set_source(PERIPH_ID_MSELECT, 0); + /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */ + clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2); /* * Our high-level clock routines are not available prior to |