arm: mxs: Add debug outputs and comments to mxs SPL source files

It is difficult to track down fail to boot issues in the mxs SPL.
Implement the following to make it easier:
 - Add debug outputs to allow tracing of SPL progress in order to track
where failure to boot occurs. DEUBUG and CONFIG_SPL_SERIAL_SUPPORT must
be defined to enable debug output in SPL
 - Add TODO comments where it is not clear if the code is doing what it
is meant to be doing, even tough the board boots properly (these comments
refer to existing code, not to any code added by this patch)

Signed-off-by: Graeme Russ <gruss@tss-engineering.com>

1 files changed, 11 insertions, 2 deletions

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
index cdfcddd824..96bd32f8ad 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c
@@ -18,6 +18,8 @@ void mxs_lradc_init(void)
 {
 	struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 
+	debug("SPL: Initialisating LRADC\n");
+
 	writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr);
 	writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr);
 	writel(LRADC_CTRL0_ONCHIP_GROUNDREF, &regs->hw_lradc_ctrl0_clr);
@@ -37,9 +39,15 @@ void mxs_lradc_enable_batt_measurement(void)
 {
 	struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 
+	debug("SPL: Enabling LRADC battery measurement\n");
+
 	/* Check if the channel is present at all. */
-	if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT))
+	if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT)) {
+		debug("SPL: LRADC channel 7 is not present - aborting\n");
 		return;
+	}
+
+	debug("SPL: LRADC channel 7 is present - configuring\n");
 
 	writel(LRADC_CTRL1_LRADC7_IRQ_EN, &regs->hw_lradc_ctrl1_clr);
 	writel(LRADC_CTRL1_LRADC7_IRQ, &regs->hw_lradc_ctrl1_clr);
@@ -65,6 +73,7 @@ void mxs_lradc_enable_batt_measurement(void)
 		100, &regs->hw_lradc_delay3);
 
 	writel(0xffffffff, &regs->hw_lradc_ch7_clr);
-
 	writel(LRADC_DELAY_KICK, &regs->hw_lradc_delay3_set);
+
+	debug("SPL: LRADC channel 7 configuration complete\n");
 }