diff options
| author | Fabio Estevam <fabio.estevam@freescale.com> | 2013-05-03 04:37:12 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2013-05-05 17:08:46 +0200 |
| commit | 39a538d9920f9422edbe339f00abe2eb7e038741 (patch) | |
| tree | f35ac1cd9d75b153d325de4275b2e106a1068cc7 /arch/arm/cpu/arm926ejs/mxs | |
| parent | b0d4bf9f0c061945e5b87150fc364e8794162a10 (diff) | |
mxs: spl_mem_init: Skip the initialization of some DRAM_CTL registers
HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as per
FSL bootlets code.
mx23 Reference Manual mark HW_DRAM_CTL27 and HW_DRAM_CTL28 as "reserved".
HW_DRAM_CTL8 is setup as the last element.
So skip the initialization of these DRAM_CTL registers.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/cpu/arm926ejs/mxs')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index df255352d0..5eacd36867 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -110,6 +110,7 @@ __weak void mxs_adjust_memory_params(uint32_t *dram_vals) { } +#ifdef CONFIG_MX28 static void initialize_dram_values(void) { int i; @@ -118,15 +119,27 @@ static void initialize_dram_values(void) for (i = 0; i < ARRAY_SIZE(dram_vals); i++) writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); +} +#else +static void initialize_dram_values(void) +{ + int i; + + mxs_adjust_memory_params(dram_vals); + + for (i = 0; i < ARRAY_SIZE(dram_vals); i++) { + if (i == 8 || i == 27 || i == 28 || i == 35) + continue; + writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); + } -#ifdef CONFIG_MX23 /* * Enable tRAS lockout in HW_DRAM_CTL08 ; it must be the last * element to be set */ writel((1 << 24), MXS_DRAM_BASE + (4 * 8)); -#endif } +#endif static void mxs_mem_init_clock(void) { |