diff options
| author | Rajeshwari Birje <rajeshwari.s@samsung.com> | 2013-12-26 09:44:21 +0530 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2013-12-30 16:50:34 +0900 |
| commit | 060c227a2861b0702e34eabe08eea9cc5bb68b45 (patch) | |
| tree | 8491031643b8226f1cb5a6f940f40e37dc8d67e8 /arch/arm/cpu/armv7/exynos/clock_init.h | |
| parent | e89278c9331143f1c5f3bc97c90aee8bce76f8b4 (diff) | |
Exynos5420: Add clock initialization for 5420
This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420
Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/cpu/armv7/exynos/clock_init.h')
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/clock_init.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h index c28ff3ab14..a875d0b48f 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init.h +++ b/arch/arm/cpu/armv7/exynos/clock_init.h @@ -10,7 +10,11 @@ #define __EXYNOS_CLOCK_INIT_H enum { +#ifdef CONFIG_EXYNOS5420 + MEM_TIMINGS_MSR_COUNT = 5, +#else MEM_TIMINGS_MSR_COUNT = 4, +#endif }; /* These are the ratio's for configuring ARM clock */ @@ -59,6 +63,18 @@ struct mem_timings { unsigned bpll_mdiv; unsigned bpll_pdiv; unsigned bpll_sdiv; + unsigned kpll_mdiv; + unsigned kpll_pdiv; + unsigned kpll_sdiv; + unsigned dpll_mdiv; + unsigned dpll_pdiv; + unsigned dpll_sdiv; + unsigned ipll_mdiv; + unsigned ipll_pdiv; + unsigned ipll_sdiv; + unsigned spll_mdiv; + unsigned spll_pdiv; + unsigned spll_sdiv; unsigned pclk_cdrex_ratio; unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT]; @@ -115,6 +131,7 @@ struct mem_timings { uint8_t send_zq_init; /* 1 to send this command */ unsigned impedance; /* drive strength impedeance */ uint8_t gate_leveling_enable; /* check gate leveling is enabled */ + uint8_t read_leveling_enable; /* check h/w read leveling is enabled */ }; /** |