k2hk: use common KS2_ prefix for all hardware definitions

Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and
add KS2_ prefix where it's needed. It requires to change names also
in places where they're used. Align lines and remove redundant
definitions in kardware-k2hk.h at the same time.

Using common KS2_ prefix helps resolve redundant redefinitions and
adds opportunity to use KS2_ definition across a project not thinking about
what SoC should be used. It's more convenient and we don't need to worry
about the SoC type in common files, hardware.h will think about that.
The hardware.h decides definitions of what SoC to use.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

5 files changed, 20 insertions, 20 deletions

diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
index bfa4c9d8f6..f905fdcf0d 100644
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ b/arch/arm/cpu/armv7/keystone/clock.c
@@ -29,11 +29,11 @@ struct pll_regs {
 };
 
 static const struct pll_regs pll_regs[] = {
-	[CORE_PLL]	= { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1},
-	[PASS_PLL]	= { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1},
-	[TETRIS_PLL]	= { K2HK_ARMPLLCTL0,  K2HK_ARMPLLCTL1},
-	[DDR3A_PLL]	= { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1},
-	[DDR3B_PLL]	= { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1},
+	[CORE_PLL]	= { KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
+	[PASS_PLL]	= { KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
+	[TETRIS_PLL]	= { KS2_ARMPLLCTL0,  KS2_ARMPLLCTL1},
+	[DDR3A_PLL]	= { KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
+	[DDR3B_PLL]	= { KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
 };
 
 /* Fout = Fref * NF(mult) / NR(prediv) / OD */
@@ -47,7 +47,7 @@ static unsigned long pll_freq_get(int pll)
 		ret = external_clk[sys_clk];
 		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
 			/* PLL mode */
-			tmp = __raw_readl(K2HK_MAINPLLCTL0);
+			tmp = __raw_readl(KS2_MAINPLLCTL0);
 			prediv = (tmp & PLL_DIV_MASK) + 1;
 			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
 				(pllctl_reg_read(pll, mult) &
@@ -61,19 +61,19 @@ static unsigned long pll_freq_get(int pll)
 		switch (pll) {
 		case PASS_PLL:
 			ret = external_clk[pa_clk];
-			reg = K2HK_PASSPLLCTL0;
+			reg = KS2_PASSPLLCTL0;
 			break;
 		case TETRIS_PLL:
 			ret = external_clk[tetris_clk];
-			reg = K2HK_ARMPLLCTL0;
+			reg = KS2_ARMPLLCTL0;
 			break;
 		case DDR3A_PLL:
 			ret = external_clk[ddr3a_clk];
-			reg = K2HK_DDR3APLLCTL0;
+			reg = KS2_DDR3APLLCTL0;
 			break;
 		case DDR3B_PLL:
 			ret = external_clk[ddr3b_clk];
-			reg = K2HK_DDR3BPLLCTL0;
+			reg = KS2_DDR3BPLLCTL0;
 			break;
 		default:
 			return 0;
@@ -214,7 +214,7 @@ void init_pll(const struct pll_init_data *data)
 		 * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
 		 * only applicable for Kepler
 		 */
-		clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+		clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
 		/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
 		setbits_le32(pll_regs[data->pll].reg1 ,
 			     PLL_PLLRST | PLLCTL_ENSAT);
@@ -255,7 +255,7 @@ void init_pll(const struct pll_init_data *data)
 		 * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
 		 * only applicable for Kepler
 		 */
-		setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN);
+		setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
 	} else {
 		setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT);
 		/*
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
index b711b810cb..2391e794e8 100644
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ b/arch/arm/cpu/armv7/keystone/ddr3.c
@@ -74,15 +74,15 @@ void ddr3_reset_ddrphy(void)
 	u32 tmp;
 
 	/* Assert DDR3A  PHY reset */
-	tmp = readl(K2HK_DDR3APLLCTL1);
+	tmp = readl(KS2_DDR3APLLCTL1);
 	tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
-	writel(tmp, K2HK_DDR3APLLCTL1);
+	writel(tmp, KS2_DDR3APLLCTL1);
 
 	/* wait 10us to catch the reset */
 	udelay(10);
 
 	/* Release DDR3A PHY reset */
-	tmp = readl(K2HK_DDR3APLLCTL1);
+	tmp = readl(KS2_DDR3APLLCTL1);
 	tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
-	__raw_writel(tmp, K2HK_DDR3APLLCTL1);
+	__raw_writel(tmp, KS2_DDR3APLLCTL1);
 }
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
index 4df5ae1cae..f4c293aa89 100644
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ b/arch/arm/cpu/armv7/keystone/init.c
@@ -15,8 +15,8 @@
 
 void chip_configuration_unlock(void)
 {
-	__raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0);
-	__raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1);
+	__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
+	__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
 }
 
 int arch_cpu_init(void)
diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/cpu/armv7/keystone/keystone.c
index 1c8c038455..11a9357db4 100644
--- a/arch/arm/cpu/armv7/keystone/keystone.c
+++ b/arch/arm/cpu/armv7/keystone/keystone.c
@@ -23,7 +23,7 @@ int cpu_to_bus(u32 *ptr, u32 length)
 {
 	u32 i;
 
-	if (!(readl(K2HK_DEVSTAT) & 0x1))
+	if (!(readl(KS2_DEVSTAT) & 0x1))
 		for (i = 0; i < length; i++, ptr++)
 			*ptr = cpu_to_be32(*ptr);
 
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c
index f3f1621d20..af858fa758 100644
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ b/arch/arm/cpu/armv7/keystone/msmc.c
@@ -58,7 +58,7 @@ struct msms_regs {
 
 void share_all_segments(int priv_id)
 {
-	struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE;
+	struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
 	int j;
 
 	for (j = 0; j < 8; j++) {