diff options
author | Tom Rini <trini@ti.com> | 2014-12-11 18:28:09 -0500 |
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committer | Tom Rini <trini@ti.com> | 2014-12-11 18:28:09 -0500 |
commit | 2c49323d5de38e119f102fa3f5fb291c4bc4e8a0 (patch) | |
tree | f64ddb2b5c393f6fac9a54dc98ea72c118922d70 /arch/arm/cpu/armv7/ls102xa/cpu.c | |
parent | 9b416a9f4ca7cf5ac4d5f7143d67edde7f7d7326 (diff) | |
parent | d0419f400af6f4bbe5c4ee5c97f6fbbdedec6cf3 (diff) |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch/arm/cpu/armv7/ls102xa/cpu.c')
-rw-r--r-- | arch/arm/cpu/armv7/ls102xa/cpu.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index b7dde45ed3..ce2d92f5a6 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -12,6 +12,8 @@ #include <netdev.h> #include <fsl_esdhc.h> +#include "fsl_epu.h" + DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_DISPLAY_CPUINFO) @@ -101,3 +103,35 @@ int cpu_eth_init(bd_t *bis) return 0; } + +int arch_cpu_init(void) +{ + void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + + /* + * After wakeup from deep sleep, Clear EPU registers + * as early as possible to prevent from possible issue. + * It's also safe to clear at normal boot. + */ + fsl_epu_clean(epu_base); + + return 0; +} + +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +/* Set the address at which the secondary core starts from.*/ +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + out_be32(&gur->scratchrw[0], addr); +} + +/* Release the secondary core from holdoff state and kick it */ +void smp_kick_all_cpus(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + out_be32(&gur->brrl, 0x2); +} +#endif |