diff options
| author | Ran Wang <ran.wang_1@nxp.com> | 2017-09-04 18:46:52 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-09-11 08:01:06 -0700 |
| commit | 83fa71189af3354cd09a56d61f3ed31ce082f51f (patch) | |
| tree | 7976e56d8ce2770598fcf8f92449f868a757f4eb /arch/arm/cpu/armv7/ls102xa | |
| parent | 15d59b5316425a21e057bff171c0459f29d00d6d (diff) | |
armv7: Add workaround for USB erratum A-009008
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature
Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv7/ls102xa')
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/Kconfig | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/soc.c | 15 |
2 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 90d99e6cc3..be30dd8442 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -2,6 +2,7 @@ config ARCH_LS1021A bool select SYS_FSL_ERRATUM_A008378 select SYS_FSL_ERRATUM_A008407 + select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 @@ -58,6 +59,11 @@ config SYS_CCI400_OFFSET Offset for CCI400 base. CCI400 base addr = CCSRBAR + CCI400_OFFSET +config SYS_FSL_ERRATUM_A009008 + bool + help + Workaround for USB PHY erratum A009008 + config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index c043b82ab7..eed06a3c7c 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -60,6 +60,18 @@ unsigned int get_soc_major_rev(void) return major; } +static void erratum_a009008(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009008 + u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; + + clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4, + 0xF << 6, + SCFG_USB_TXVREFTUNE << 6); +#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */ +} + + void s_init(void) { } @@ -147,6 +159,9 @@ int arch_soc_init(void) */ out_be32(&scfg->eddrtqcfg, 0x63b20042); + /* Erratum */ + erratum_a009008(); + return 0; } |