diff options
| author | Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | 2013-01-30 11:19:17 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2013-02-12 13:52:31 +0100 |
| commit | b42b5b7a243ab3923fd80ab03f950f036b6e1329 (patch) | |
| tree | 2dec05cd0a9861dd8732da17cc05bc843c2c7765 /arch/arm/cpu/armv7/mx6 | |
| parent | 1791b1f97f71bb4f110ca851ab10479640b7bc05 (diff) | |
imx: mx6q DDR3 init: Fix MR0.PPD
MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which
is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28].
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6')
0 files changed, 0 insertions, 0 deletions