diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2012-05-22 00:03:26 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-07-07 14:07:24 +0200 |
| commit | 753bae8c5dd4ba92a39b06ea9a551be962053f93 (patch) | |
| tree | 39a9614f4f53620d8f5d3c42aa7d98f1f04b46f1 /arch/arm/cpu/armv7/omap-common/emif-common.c | |
| parent | 784ab7c545d25288a82216d18e2b0ca3beae470b (diff) | |
OMAP5: DPLL core lock for OMAP5432
No need to Unlock DPLL initially.
DDR3 can work at normal OPP from initialozation
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap-common/emif-common.c')
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/emif-common.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 846511d03b..23cf6199eb 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1232,6 +1232,7 @@ void dmm_init(u32 base) void sdram_init(void) { u32 in_sdram, size_prog, size_detect; + u32 omap_rev = omap_revision(); debug(">>sdram_init()\n"); @@ -1241,9 +1242,12 @@ void sdram_init(void) in_sdram = running_from_sdram(); debug("in_sdram = %d\n", in_sdram); - if (!in_sdram) - bypass_dpll(&prcm->cm_clkmode_dpll_core); - + if (!in_sdram) { + if (omap_rev != OMAP5432_ES1_0) + bypass_dpll(&prcm->cm_clkmode_dpll_core); + else + writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl); + } do_sdram_init(EMIF1_BASE); do_sdram_init(EMIF2_BASE); @@ -1255,7 +1259,8 @@ void sdram_init(void) } /* for the shadow registers to take effect */ - freq_update_core(); + if (omap_rev != OMAP5432_ES1_0) + freq_update_core(); /* Do some testing after the init */ if (!in_sdram) { |