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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-11 22:24:28 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2013-05-11 22:24:28 +0200 |
| commit | cac423a730d3506154744485af1bbc1cd3a1e6a8 (patch) | |
| tree | 358b627972d9125de573c623f33e2da789f1de51 /arch/arm/cpu/armv7/omap-common/emif-common.c | |
| parent | c1b43ac7699640c8086bd73faa798bc9722d32c9 (diff) | |
| parent | 47c6ea076eb51e624f8744d93db5cd70b97dc25d (diff) | |
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/cpu/armv7/omap-common/emif-common.c')
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/emif-common.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index cdb4439721..11e830a533 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1075,6 +1075,11 @@ static void do_sdram_init(u32 base) else ddr3_init(base, regs); } + if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) { + set_lpmode_selfrefresh(base); + emif_reset_phy(base); + ddr3_leveling(base, regs); + } /* Write to the shadow registers */ emif_update_timings(base, regs); @@ -1262,10 +1267,10 @@ void sdram_init(void) in_sdram = running_from_sdram(); debug("in_sdram = %d\n", in_sdram); - if (!(in_sdram || warm_reset())) { - if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) + if (!in_sdram) { + if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset()) bypass_dpll((*prcm)->cm_clkmode_dpll_core); - else + else if (sdram_type == EMIF_SDRAM_TYPE_DDR3) writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); } |