diff options
| author | Siarhei Siamashka <siarhei.siamashka@gmail.com> | 2014-08-03 05:32:41 +0300 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2014-08-12 08:42:32 +0200 |
| commit | e626d2d446996b4b1cd16bf65b42c080985d8a84 (patch) | |
| tree | 5fbf9ee32c38d0ca8b3a6576c0f031975659e0de /arch/arm/cpu/armv7/omap3/spl_id_nand.c | |
| parent | f2577967738f923571b7156ad46ef91d9fa8d9f8 (diff) | |
sunxi: dram: Respect the DDR3 reset timing requirements
The RESET pin needs to be kept low for at least 200 us according
to the DDR3 spec. So just do it the right way.
This issue did not cause any visible major problems earlier, because
the DRAM RESET pin is usually already low after the board reset. And
the time gap before reaching the sunxi u-boot DRAM initialization
code appeared to be sufficient.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap3/spl_id_nand.c')
0 files changed, 0 insertions, 0 deletions