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authorTom Rini <trini@konsulko.com>2016-11-07 21:34:54 -0500
committerTom Rini <trini@konsulko.com>2016-11-21 14:07:29 -0500
commit983e37007da506e8145f9b3a9e1dce5c11116fb0 (patch)
treec1d5449e1c56e17f22bb4f75b6f11336abca41a4 /arch/arm/cpu/armv7/omap3
parent272686eb7576c02df4616bcf893fde993e7ba57e (diff)
arm: Introduce arch/arm/mach-omap2 for OMAP2 derivative platforms
This moves what was in arch/arm/cpu/armv7/omap-common in to arch/arm/mach-omap2 and moves arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2 as subdirectories. All refernces to the former locations are updated to the current locations. For the logic to decide what our outputs are, consolidate the tests into a single config.mk rather than including 4. Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap3')
-rw-r--r--arch/arm/cpu/armv7/omap3/Kconfig154
-rw-r--r--arch/arm/cpu/armv7/omap3/Makefile21
-rw-r--r--arch/arm/cpu/armv7/omap3/am35x_musb.c61
-rw-r--r--arch/arm/cpu/armv7/omap3/board.c434
-rw-r--r--arch/arm/cpu/armv7/omap3/boot.c104
-rw-r--r--arch/arm/cpu/armv7/omap3/clock.c799
-rw-r--r--arch/arm/cpu/armv7/omap3/config.mk15
-rw-r--r--arch/arm/cpu/armv7/omap3/emac.c29
-rw-r--r--arch/arm/cpu/armv7/omap3/emif4.c165
-rw-r--r--arch/arm/cpu/armv7/omap3/lowlevel_init.S476
-rw-r--r--arch/arm/cpu/armv7/omap3/sdrc.c241
-rw-r--r--arch/arm/cpu/armv7/omap3/spl_id_nand.c57
-rw-r--r--arch/arm/cpu/armv7/omap3/sys_info.c343
13 files changed, 0 insertions, 2899 deletions
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
deleted file mode 100644
index 7d884a237b..0000000000
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ /dev/null
@@ -1,154 +0,0 @@
-if OMAP34XX
-
-config SPL_EXT_SUPPORT
- default y
-
-config SPL_FAT_SUPPORT
- default y
-
-config SPL_GPIO_SUPPORT
- default y
-
-config SPL_I2C_SUPPORT
- default y
-
-config SPL_LIBCOMMON_SUPPORT
- default y
-
-config SPL_LIBDISK_SUPPORT
- default y
-
-config SPL_LIBGENERIC_SUPPORT
- default y
-
-config SPL_MMC_SUPPORT
- default y
-
-config SPL_NAND_SUPPORT
- default y
-
-config SPL_POWER_SUPPORT
- default y
-
-config SPL_SERIAL_SUPPORT
- default y
-
-choice
- prompt "OMAP3 board select"
- optional
-
-config TARGET_AM3517_EVM
- bool "AM3517 EVM"
-
-config TARGET_MT_VENTOUX
- bool "TeeJet Mt.Ventoux"
-
-config TARGET_OMAP3_BEAGLE
- bool "TI OMAP3 BeagleBoard"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_CM_T35
- bool "CompuLab CM-T3530 and CM-T3730 boards"
-
-config TARGET_CM_T3517
- bool "CompuLab CM-T3517 boards"
-
-config TARGET_DEVKIT8000
- bool "TimLL OMAP3 Devkit8000"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_OMAP3_EVM
- bool "TI OMAP3 EVM"
-
-config TARGET_OMAP3_IGEP00X0
- bool "IGEP"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_OMAP3_OVERO
- bool "OMAP35xx Gumstix Overo"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_OMAP3_ZOOM1
- bool "TI Zoom1"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_AM3517_CRANE
- bool "am3517_crane"
-
-config TARGET_OMAP3_PANDORA
- bool "OMAP3 Pandora"
-
-config TARGET_ECO5PK
- bool "ECO5PK"
-
-config TARGET_TRICORDER
- bool "Tricorder"
-
-config TARGET_MCX
- bool "MCX"
-
-config TARGET_OMAP3_LOGIC
- bool "OMAP3 Logic"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_NOKIA_RX51
- bool "Nokia RX51"
-
-config TARGET_TAO3530
- bool "TAO3530"
-
-config TARGET_TWISTER
- bool "Twister"
-
-config TARGET_OMAP3_CAIRO
- bool "QUIPOS CAIRO"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-config TARGET_SNIPER
- bool "LG Optimus Black"
- select DM
- select DM_SERIAL
- select DM_GPIO
-
-endchoice
-
-config SYS_SOC
- default "omap3"
-
-source "board/logicpd/am3517evm/Kconfig"
-source "board/teejet/mt_ventoux/Kconfig"
-source "board/ti/beagle/Kconfig"
-source "board/compulab/cm_t35/Kconfig"
-source "board/compulab/cm_t3517/Kconfig"
-source "board/timll/devkit8000/Kconfig"
-source "board/ti/evm/Kconfig"
-source "board/isee/igep00x0/Kconfig"
-source "board/overo/Kconfig"
-source "board/logicpd/zoom1/Kconfig"
-source "board/ti/am3517crane/Kconfig"
-source "board/pandora/Kconfig"
-source "board/8dtech/eco5pk/Kconfig"
-source "board/corscience/tricorder/Kconfig"
-source "board/htkw/mcx/Kconfig"
-source "board/logicpd/omap3som/Kconfig"
-source "board/nokia/rx51/Kconfig"
-source "board/technexion/tao3530/Kconfig"
-source "board/technexion/twister/Kconfig"
-source "board/quipos/cairo/Kconfig"
-source "board/lg/sniper/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile
deleted file mode 100644
index b2fce966d9..0000000000
--- a/arch/arm/cpu/armv7/omap3/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := lowlevel_init.o
-
-obj-y += board.o
-obj-y += boot.o
-obj-y += clock.o
-obj-y += sys_info.o
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o
-endif
-
-obj-$(CONFIG_DRIVER_TI_EMAC) += emac.o
-obj-$(CONFIG_EMIF4) += emif4.o
-obj-$(CONFIG_SDRC) += sdrc.o
-obj-$(CONFIG_USB_MUSB_AM35X) += am35x_musb.o
diff --git a/arch/arm/cpu/armv7/omap3/am35x_musb.c b/arch/arm/cpu/armv7/omap3/am35x_musb.c
deleted file mode 100644
index 74dd105eb6..0000000000
--- a/arch/arm/cpu/armv7/omap3/am35x_musb.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file configures the internal USB PHY in AM35X.
- *
- * Copyright (C) 2012 Ilya Yanok <ilya.yanok@gmail.com>
- *
- * Based on omap_phy_internal.c code from Linux by
- * Hema HK <hemahk@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/am35x_def.h>
-
-void am35x_musb_reset(void)
-{
- /* Reset the musb interface */
- clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
- 0, USBOTGSS_SW_RST);
- clrsetbits_le32(&am35x_scm_general_regs->ip_sw_reset,
- USBOTGSS_SW_RST, 0);
-}
-
-void am35x_musb_phy_power(u8 on)
-{
- unsigned long start = get_timer(0);
-
- if (on) {
- /*
- * Start the on-chip PHY and its PLL.
- */
- clrsetbits_le32(&am35x_scm_general_regs->devconf2,
- CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN,
- CONF2_PHY_PLLON);
-
- debug("Waiting for PHY clock good...\n");
- while (!(readl(&am35x_scm_general_regs->devconf2)
- & CONF2_PHYCLKGD)) {
-
- if (get_timer(start) > CONFIG_SYS_HZ / 10) {
- printf("musb PHY clock good timed out\n");
- break;
- }
- }
- } else {
- /*
- * Power down the on-chip PHY.
- */
- clrsetbits_le32(&am35x_scm_general_regs->devconf2,
- CONF2_PHY_PLLON,
- CONF2_PHYPWRDN | CONF2_OTGPWRDN);
- }
-}
-
-void am35x_musb_clear_irq(void)
-{
- clrsetbits_le32(&am35x_scm_general_regs->lvl_intr_clr,
- 0, USBOTGSS_INT_CLR);
- readl(&am35x_scm_general_regs->lvl_intr_clr);
-}
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
deleted file mode 100644
index 5f5597772b..0000000000
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ /dev/null
@@ -1,434 +0,0 @@
-/*
- *
- * Common board functions for OMAP3 based boards.
- *
- * (C) Copyright 2004-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <dm.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-#include <asm/cache.h>
-#include <asm/armv7.h>
-#include <asm/gpio.h>
-#include <asm/omap_common.h>
-#include <linux/compiler.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Declarations */
-extern omap3_sysinfo sysinfo;
-#ifndef CONFIG_SYS_L2CACHE_OFF
-static void omap3_invalidate_l2_cache_secure(void);
-#endif
-
-#ifdef CONFIG_DM_GPIO
-static const struct omap_gpio_platdata omap34xx_gpio[] = {
- { 0, OMAP34XX_GPIO1_BASE },
- { 1, OMAP34XX_GPIO2_BASE },
- { 2, OMAP34XX_GPIO3_BASE },
- { 3, OMAP34XX_GPIO4_BASE },
- { 4, OMAP34XX_GPIO5_BASE },
- { 5, OMAP34XX_GPIO6_BASE },
-};
-
-U_BOOT_DEVICES(am33xx_gpios) = {
- { "gpio_omap", &omap34xx_gpio[0] },
- { "gpio_omap", &omap34xx_gpio[1] },
- { "gpio_omap", &omap34xx_gpio[2] },
- { "gpio_omap", &omap34xx_gpio[3] },
- { "gpio_omap", &omap34xx_gpio[4] },
- { "gpio_omap", &omap34xx_gpio[5] },
-};
-
-#else
-
-static const struct gpio_bank gpio_bank_34xx[6] = {
- { (void *)OMAP34XX_GPIO1_BASE },
- { (void *)OMAP34XX_GPIO2_BASE },
- { (void *)OMAP34XX_GPIO3_BASE },
- { (void *)OMAP34XX_GPIO4_BASE },
- { (void *)OMAP34XX_GPIO5_BASE },
- { (void *)OMAP34XX_GPIO6_BASE },
-};
-
-const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
-
-#endif
-
-/******************************************************************************
- * Routine: secure_unlock
- * Description: Setup security registers for access
- * (GP Device only)
- *****************************************************************************/
-void secure_unlock_mem(void)
-{
- struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
- struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
- struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
- struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
- struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
-
- /* Protection Module Register Target APE (PM_RT) */
- writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
- writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
- writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
- writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
-
- writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
- writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
- writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
-
- writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
- writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
- writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
- writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
-
- /* IVA Changes */
- writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
- writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
- writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
-
- /* SDRC region 0 public */
- writel(UNLOCK_1, &sms_base->rg_att0);
-}
-
-/******************************************************************************
- * Routine: secureworld_exit()
- * Description: If chip is EMU and boot type is external
- * configure secure registers and exit secure world
- * general use.
- *****************************************************************************/
-void secureworld_exit(void)
-{
- unsigned long i;
-
- /* configure non-secure access control register */
- __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
- /* enabling co-processor CP10 and CP11 accesses in NS world */
- __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
- /*
- * allow allocation of locked TLBs and L2 lines in NS world
- * allow use of PLE registers in NS world also
- */
- __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
- __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
-
- /* Enable ASA in ACR register */
- __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
- __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
- __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
-
- /* Exiting secure world */
- __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
- __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
- __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
-}
-
-/******************************************************************************
- * Routine: try_unlock_sram()
- * Description: If chip is GP/EMU(special) type, unlock the SRAM for
- * general use.
- *****************************************************************************/
-void try_unlock_memory(void)
-{
- int mode;
- int in_sdram = is_running_in_sdram();
-
- /*
- * if GP device unlock device SRAM for general use
- * secure code breaks for Secure/Emulation device - HS/E/T
- */
- mode = get_device_type();
- if (mode == GP_DEVICE)
- secure_unlock_mem();
-
- /*
- * If device is EMU and boot is XIP external booting
- * Unlock firewalls and disable L2 and put chip
- * out of secure world
- *
- * Assuming memories are unlocked by the demon who put us in SDRAM
- */
- if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
- && (!in_sdram)) {
- secure_unlock_mem();
- secureworld_exit();
- }
-
- return;
-}
-
-/******************************************************************************
- * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- * - Called path is with SRAM stack.
- *****************************************************************************/
-void s_init(void)
-{
- watchdog_init();
-
- try_unlock_memory();
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
- /* Invalidate L2-cache from secure mode */
- omap3_invalidate_l2_cache_secure();
-#endif
-
- set_muxconf_regs();
- sdelay(100);
-
- prcm_init();
-
- per_clocks_enable();
-
-#ifdef CONFIG_USB_EHCI_OMAP
- ehci_clocks_enable();
-#endif
-}
-
-#ifdef CONFIG_SPL_BUILD
-void board_init_f(ulong dummy)
-{
- mem_init();
-}
-#endif
-
-/*
- * Routine: misc_init_r
- * Description: A basic misc_init_r that just displays the die ID
- */
-int __weak misc_init_r(void)
-{
- omap_die_id_display();
-
- return 0;
-}
-
-/******************************************************************************
- * Routine: wait_for_command_complete
- * Description: Wait for posting to finish on watchdog
- *****************************************************************************/
-static void wait_for_command_complete(struct watchdog *wd_base)
-{
- int pending = 1;
- do {
- pending = readl(&wd_base->wwps);
- } while (pending);
-}
-
-/******************************************************************************
- * Routine: watchdog_init
- * Description: Shut down watch dogs
- *****************************************************************************/
-void watchdog_init(void)
-{
- struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-
- /*
- * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
- * either taken care of by ROM (HS/EMU) or not accessible (GP).
- * We need to take care of WD2-MPU or take a PRCM reset. WD3
- * should not be running and does not generate a PRCM reset.
- */
-
- setbits_le32(&prcm_base->fclken_wkup, 0x20);
- setbits_le32(&prcm_base->iclken_wkup, 0x20);
- wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
-
- writel(WD_UNLOCK1, &wd2_base->wspr);
- wait_for_command_complete(wd2_base);
- writel(WD_UNLOCK2, &wd2_base->wspr);
-}
-
-/******************************************************************************
- * Dummy function to handle errors for EABI incompatibility
- *****************************************************************************/
-void abort(void)
-{
-}
-
-#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
-/******************************************************************************
- * OMAP3 specific command to switch between NAND HW and SW ecc
- *****************************************************************************/
-static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- if (argc < 2 || argc > 3)
- goto usage;
-
- if (strncmp(argv[1], "hw", 2) == 0) {
- if (argc == 2) {
- omap_nand_switch_ecc(1, 1);
- } else {
- if (strncmp(argv[2], "hamming", 7) == 0)
- omap_nand_switch_ecc(1, 1);
- else if (strncmp(argv[2], "bch8", 4) == 0)
- omap_nand_switch_ecc(1, 8);
- else if (strncmp(argv[2], "bch16", 5) == 0)
- omap_nand_switch_ecc(1, 16);
- else
- goto usage;
- }
- } else if (strncmp(argv[1], "sw", 2) == 0) {
- if (argc == 2) {
- omap_nand_switch_ecc(0, 1);
- } else {
- if (strncmp(argv[2], "hamming", 7) == 0)
- omap_nand_switch_ecc(0, 1);
- else if (strncmp(argv[2], "bch8", 4) == 0)
- omap_nand_switch_ecc(0, 8);
- else
- goto usage;
- }
- } else {
- goto usage;
- }
-
- return 0;
-
-usage:
- printf ("Usage: nandecc %s\n", cmdtp->usage);
- return 1;
-}
-
-U_BOOT_CMD(
- nandecc, 3, 1, do_switch_ecc,
- "switch OMAP3 NAND ECC calculation algorithm",
- "hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
- " and 8-bit/16-bit BCH\n"
- " ecc calculation (second parameter may"
- " be omitted).\n"
- "nandecc sw - Switch to NAND software ecc algorithm."
-);
-
-#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
-
-#ifdef CONFIG_DISPLAY_BOARDINFO
-/**
- * Print board information
- */
-int checkboard (void)
-{
- char *mem_s ;
-
- if (is_mem_sdr())
- mem_s = "mSDR";
- else
- mem_s = "LPDDR";
-
- printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
- sysinfo.nand_string);
-
- return 0;
-}
-#endif /* CONFIG_DISPLAY_BOARDINFO */
-
-static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
-{
- u32 i, num_params = *parameters;
- u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
-
- /*
- * copy the parameters to an un-cached area to avoid coherency
- * issues
- */
- for (i = 0; i < num_params; i++) {
- __raw_writel(*parameters, sram_scratch_space);
- parameters++;
- sram_scratch_space++;
- }
-
- /* Now make the PPA call */
- do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
-}
-
-void __weak omap3_set_aux_cr_secure(u32 acr)
-{
- struct emu_hal_params emu_romcode_params;
-
- emu_romcode_params.num_params = 1;
- emu_romcode_params.param1 = acr;
- omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
- (u32 *)&emu_romcode_params);
-}
-
-void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
- u32 cpu_variant, u32 cpu_rev)
-{
- /* Write ACR - affects secure banked bits */
- if (get_device_type() == GP_DEVICE)
- omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
- else
- omap3_set_aux_cr_secure(acr);
-
- /* Write ACR - affects non-secure banked bits - some erratas need it */
- asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
-}
-
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
-{
- u32 acr;
-
- /* Read ACR */
- asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
- acr &= ~clear_bits;
- acr |= set_bits;
- v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
-
-}
-
-/* Invalidate the entire L2 cache from secure mode */
-static void omap3_invalidate_l2_cache_secure(void)
-{
- if (get_device_type() == GP_DEVICE) {
- omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
- } else {
- struct emu_hal_params emu_romcode_params;
- emu_romcode_params.num_params = 1;
- emu_romcode_params.param1 = 0;
- omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
- (u32 *)&emu_romcode_params);
- }
-}
-
-void v7_outer_cache_enable(void)
-{
-
- /*
- * Set L2EN
- * On some revisions L2EN bit is banked on some revisions it's not
- * No harm in setting both banked bits(in fact this is required
- * by an erratum)
- */
- omap3_update_aux_cr(0x2, 0);
-}
-
-void omap3_outer_cache_disable(void)
-{
- /*
- * Clear L2EN
- * On some revisions L2EN bit is banked on some revisions it's not
- * No harm in clearing both banked bits(in fact this is required
- * by an erratum)
- */
- omap3_update_aux_cr(0, 0x2);
-}
-#endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/arch/arm/cpu/armv7/omap3/boot.c b/arch/arm/cpu/armv7/omap3/boot.c
deleted file mode 100644
index 64b242b752..0000000000
--- a/arch/arm/cpu/armv7/omap3/boot.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * OMAP3 boot
- *
- * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <spl.h>
-
-static u32 boot_devices[] = {
- BOOT_DEVICE_ONENAND,
- BOOT_DEVICE_NAND,
- BOOT_DEVICE_ONENAND,
- BOOT_DEVICE_MMC2,
- BOOT_DEVICE_ONENAND,
- BOOT_DEVICE_MMC2,
- BOOT_DEVICE_MMC1,
- BOOT_DEVICE_XIP,
- BOOT_DEVICE_XIPWAIT,
- BOOT_DEVICE_MMC2,
- BOOT_DEVICE_XIP,
- BOOT_DEVICE_XIPWAIT,
- BOOT_DEVICE_NAND,
- BOOT_DEVICE_XIP,
- BOOT_DEVICE_XIPWAIT,
- BOOT_DEVICE_NAND,
- BOOT_DEVICE_ONENAND,
- BOOT_DEVICE_MMC2,
- BOOT_DEVICE_MMC1,
- BOOT_DEVICE_XIP,
- BOOT_DEVICE_XIPWAIT,
- BOOT_DEVICE_NAND,
- BOOT_DEVICE_ONENAND,
- BOOT_DEVICE_MMC2,
- BOOT_DEVICE_MMC1,
- BOOT_DEVICE_XIP,
- BOOT_DEVICE_XIPWAIT,
- BOOT_DEVICE_NAND,
- BOOT_DEVICE_MMC2_2,
-};
-
-u32 omap_sys_boot_device(void)
-{
- struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
- u32 sys_boot;
-
- /* Grab the first 5 bits of the status register for SYS_BOOT. */
- sys_boot = readl(&ctrl_base->status) & ((1 << 5) - 1);
-
- if (sys_boot >= (sizeof(boot_devices) / sizeof(u32)))
- return BOOT_DEVICE_NONE;
-
- return boot_devices[sys_boot];
-}
-
-int omap_reboot_mode(char *mode, unsigned int length)
-{
- u32 reboot_mode;
- char c;
-
- if (length < 2)
- return -1;
-
- reboot_mode = readl((u32 *)(OMAP34XX_SCRATCHPAD +
- OMAP_REBOOT_REASON_OFFSET));
-
- c = (reboot_mode >> 24) & 0xff;
- if (c != 'B')
- return -1;
-
- c = (reboot_mode >> 16) & 0xff;
- if (c != 'M')
- return -1;
-
- c = reboot_mode & 0xff;
-
- mode[0] = c;
- mode[1] = '\0';
-
- return 0;
-}
-
-int omap_reboot_mode_clear(void)
-{
- writel(0, (u32 *)(OMAP34XX_SCRATCHPAD + OMAP_REBOOT_REASON_OFFSET));
-
- return 0;
-}
-
-int omap_reboot_mode_store(char *mode)
-{
- u32 reboot_mode;
-
- reboot_mode = 'B' << 24 | 'M' << 16 | mode[0];
-
- writel(reboot_mode, (u32 *)(OMAP34XX_SCRATCHPAD +
- OMAP_REBOOT_REASON_OFFSET));
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
deleted file mode 100644
index 006969e780..0000000000
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ /dev/null
@@ -1,799 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Manikandan Pillai <mani.pillai@ti.com>
- *
- * Derived from Beagle Board and OMAP3 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clocks_omap3.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <environment.h>
-#include <command.h>
-
-/******************************************************************************
- * get_sys_clk_speed() - determine reference oscillator speed
- * based on known 32kHz clock and gptimer.
- *****************************************************************************/
-u32 get_osc_clk_speed(void)
-{
- u32 start, cstart, cend, cdiff, cdiv, val;
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- struct prm *prm_base = (struct prm *)PRM_BASE;
- struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
- struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
-
- val = readl(&prm_base->clksrc_ctrl);
-
- if (val & SYSCLKDIV_2)
- cdiv = 2;
- else
- cdiv = 1;
-
- /* enable timer2 */
- val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
-
- /* select sys_clk for GPT1 */
- writel(val, &prcm_base->clksel_wkup);
-
- /* Enable I and F Clocks for GPT1 */
- val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
- writel(val, &prcm_base->iclken_wkup);
-
- val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
- writel(val, &prcm_base->fclken_wkup);
-
- writel(0, &gpt1_base->tldr); /* start counting at 0 */
- writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
-
- /* enable 32kHz source, determine sys_clk via gauging */
-
- /* start time in 20 cycles */
- start = 20 + readl(&s32k_base->s32k_cr);
-
- /* dead loop till start time */
- while (readl(&s32k_base->s32k_cr) < start);
-
- /* get start sys_clk count */
- cstart = readl(&gpt1_base->tcrr);
-
- /* wait for 40 cycles */
- while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
- cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
- cdiff = cend - cstart; /* get elapsed ticks */
- cdiff *= cdiv;
-
- /* based on number of ticks assign speed */
- if (cdiff > 19000)
- return S38_4M;
- else if (cdiff > 15200)
- return S26M;
- else if (cdiff > 13000)
- return S24M;
- else if (cdiff > 9000)
- return S19_2M;
- else if (cdiff > 7600)
- return S13M;
- else
- return S12M;
-}
-
-/******************************************************************************
- * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
- * input oscillator clock frequency.
- *****************************************************************************/
-void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
-{
- switch(osc_clk) {
- case S38_4M:
- *sys_clkin_sel = 4;
- break;
- case S26M:
- *sys_clkin_sel = 3;
- break;
- case S19_2M:
- *sys_clkin_sel = 2;
- break;
- case S13M:
- *sys_clkin_sel = 1;
- break;
- case S12M:
- default:
- *sys_clkin_sel = 0;
- }
-}
-
-/*
- * OMAP34XX/35XX specific functions
- */
-
-static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_core_dpll_param();
- void (*f_lock_pll) (u32, u32, u32, u32);
- int xip_safe, p0, p1, p2, p3;
-
- xip_safe = is_running_in_sram();
-
- /* Moving to the right sysclk and ES rev base */
- ptr = ptr + (3 * clk_index) + sil_index;
-
- if (xip_safe) {
- /*
- * CORE DPLL
- */
- clrsetbits_le32(&prcm_base->clken_pll,
- 0x00000007, PLL_FAST_RELOCK_BYPASS);
- wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
- LDELAY);
-
- /*
- * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
- * work. write another value and then default value.
- */
-
- /* CM_CLKSEL1_EMU[DIV_DPLL3] */
- clrsetbits_le32(&prcm_base->clksel1_emu,
- 0x001F0000, (CORE_M3X2 + 1) << 16) ;
- clrsetbits_le32(&prcm_base->clksel1_emu,
- 0x001F0000, CORE_M3X2 << 16);
-
- /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- clrsetbits_le32(&prcm_base->clksel1_pll,
- 0xF8000000, ptr->m2 << 27);
-
- /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- clrsetbits_le32(&prcm_base->clksel1_pll,
- 0x07FF0000, ptr->m << 16);
-
- /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- clrsetbits_le32(&prcm_base->clksel1_pll,
- 0x00007F00, ptr->n << 8);
-
- /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
-
- /* SSI */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x00000F00, CORE_SSI_DIV << 8);
- /* FSUSB */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x00000030, CORE_FUSB_DIV << 4);
- /* L4 */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x0000000C, CORE_L4_DIV << 2);
- /* L3 */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x00000003, CORE_L3_DIV);
- /* GFX */
- clrsetbits_le32(&prcm_base->clksel_gfx,
- 0x00000007, GFX_DIV);
- /* RESET MGR */
- clrsetbits_le32(&prcm_base->clksel_wkup,
- 0x00000006, WKUP_RSM << 1);
- /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- clrsetbits_le32(&prcm_base->clken_pll,
- 0x000000F0, ptr->fsel << 4);
- /* LOCK MODE */
- clrsetbits_le32(&prcm_base->clken_pll,
- 0x00000007, PLL_LOCK);
-
- wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
- LDELAY);
- } else if (is_running_in_flash()) {
- /*
- * if running from flash, jump to small relocated code
- * area in SRAM.
- */
- f_lock_pll = (void *) (SRAM_CLK_CODE);
-
- p0 = readl(&prcm_base->clken_pll);
- clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
- /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
-
- p1 = readl(&prcm_base->clksel1_pll);
- /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
- /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
- /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
- /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- clrbits_le32(&p1, 0x00000040);
-
- p2 = readl(&prcm_base->clksel_core);
- /* SSI */
- clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
- /* FSUSB */
- clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
- /* L4 */
- clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
- /* L3 */
- clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
-
- p3 = (u32)&prcm_base->idlest_ckgen;
-
- (*f_lock_pll) (p0, p1, p2, p3);
- }
-}
-
-static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_per_dpll_param();
-
- /* Moving it to the right sysclk base */
- ptr = ptr + clk_index;
-
- /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
- clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
- wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
-
- /*
- * Errata 1.50 Workaround for OMAP3 ES1.0 only
- * If using default divisors, write default divisor + 1
- * and then the actual divisor value
- */
- /* M6 */
- clrsetbits_le32(&prcm_base->clksel1_emu,
- 0x1F000000, (PER_M6X2 + 1) << 24);
- clrsetbits_le32(&prcm_base->clksel1_emu,
- 0x1F000000, PER_M6X2 << 24);
- /* M5 */
- clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1));
- clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2);
- /* M4 */
- clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1));
- clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2);
- /* M3 */
- clrsetbits_le32(&prcm_base->clksel_dss,
- 0x00001F00, (PER_M3X2 + 1) << 8);
- clrsetbits_le32(&prcm_base->clksel_dss,
- 0x00001F00, PER_M3X2 << 8);
- /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
- clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1));
- clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
- /* Workaround end */
-
- /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
- clrsetbits_le32(&prcm_base->clksel2_pll,
- 0x0007FF00, ptr->m << 8);
-
- /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
- clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
-
- /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
- clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20);
-
- /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
- clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
- wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
-}
-
-static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
-
- /* Moving it to the right sysclk base */
- ptr = ptr + clk_index;
-
- /* PER2 DPLL (DPLL5) */
- clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
- wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
- /* set M2 (usbtll_fck) */
- clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
- /* set m (11-bit multiplier) */
- clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
- /* set n (7-bit divider)*/
- clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
- /* FREQSEL */
- clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4);
- /* lock mode */
- clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
- wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
-}
-
-static void mpu_init_34xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
-
- /* Moving to the right sysclk and ES rev base */
- ptr = ptr + (3 * clk_index) + sil_index;
-
- /* MPU DPLL (unlocked already) */
-
- /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
- clrsetbits_le32(&prcm_base->clksel2_pll_mpu,
- 0x0000001F, ptr->m2);
-
- /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
- clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
- 0x0007FF00, ptr->m << 8);
-
- /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
- clrsetbits_le32(&prcm_base->clksel1_pll_mpu,
- 0x0000007F, ptr->n);
-
- /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
- clrsetbits_le32(&prcm_base->clken_pll_mpu,
- 0x000000F0, ptr->fsel << 4);
-}
-
-static void iva_init_34xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
-
- /* Moving to the right sysclk and ES rev base */
- ptr = ptr + (3 * clk_index) + sil_index;
-
- /* IVA DPLL */
- /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
- clrsetbits_le32(&prcm_base->clken_pll_iva2,
- 0x00000007, PLL_STOP);
- wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
-
- /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
- clrsetbits_le32(&prcm_base->clksel2_pll_iva2,
- 0x0000001F, ptr->m2);
-
- /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
- clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
- 0x0007FF00, ptr->m << 8);
-
- /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
- clrsetbits_le32(&prcm_base->clksel1_pll_iva2,
- 0x0000007F, ptr->n);
-
- /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
- clrsetbits_le32(&prcm_base->clken_pll_iva2,
- 0x000000F0, ptr->fsel << 4);
-
- /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
- clrsetbits_le32(&prcm_base->clken_pll_iva2,
- 0x00000007, PLL_LOCK);
-
- wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
-}
-
-/*
- * OMAP3630 specific functions
- */
-
-static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
- void (*f_lock_pll) (u32, u32, u32, u32);
- int xip_safe, p0, p1, p2, p3;
-
- xip_safe = is_running_in_sram();
-
- /* Moving it to the right sysclk base */
- ptr += clk_index;
-
- if (xip_safe) {
- /* CORE DPLL */
-
- /* Select relock bypass: CM_CLKEN_PLL[0:2] */
- clrsetbits_le32(&prcm_base->clken_pll,
- 0x00000007, PLL_FAST_RELOCK_BYPASS);
- wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
- LDELAY);
-
- /* CM_CLKSEL1_EMU[DIV_DPLL3] */
- clrsetbits_le32(&prcm_base->clksel1_emu,
- 0x001F0000, CORE_M3X2 << 16);
-
- /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- clrsetbits_le32(&prcm_base->clksel1_pll,
- 0xF8000000, ptr->m2 << 27);
-
- /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- clrsetbits_le32(&prcm_base->clksel1_pll,
- 0x07FF0000, ptr->m << 16);
-
- /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- clrsetbits_le32(&prcm_base->clksel1_pll,
- 0x00007F00, ptr->n << 8);
-
- /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- clrbits_le32(&prcm_base->clksel1_pll, 0x00000040);
-
- /* SSI */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x00000F00, CORE_SSI_DIV << 8);
- /* FSUSB */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x00000030, CORE_FUSB_DIV << 4);
- /* L4 */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x0000000C, CORE_L4_DIV << 2);
- /* L3 */
- clrsetbits_le32(&prcm_base->clksel_core,
- 0x00000003, CORE_L3_DIV);
- /* GFX */
- clrsetbits_le32(&prcm_base->clksel_gfx,
- 0x00000007, GFX_DIV_36X);
- /* RESET MGR */
- clrsetbits_le32(&prcm_base->clksel_wkup,
- 0x00000006, WKUP_RSM << 1);
- /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- clrsetbits_le32(&prcm_base->clken_pll,
- 0x000000F0, ptr->fsel << 4);
- /* LOCK MODE */
- clrsetbits_le32(&prcm_base->clken_pll,
- 0x00000007, PLL_LOCK);
-
- wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
- LDELAY);
- } else if (is_running_in_flash()) {
- /*
- * if running from flash, jump to small relocated code
- * area in SRAM.
- */
- f_lock_pll = (void *) (SRAM_CLK_CODE);
-
- p0 = readl(&prcm_base->clken_pll);
- clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS);
- /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
- clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4);
-
- p1 = readl(&prcm_base->clksel1_pll);
- /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
- clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);
- /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
- clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16);
- /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
- clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8);
- /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
- clrbits_le32(&p1, 0x00000040);
-
- p2 = readl(&prcm_base->clksel_core);
- /* SSI */
- clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8);
- /* FSUSB */
- clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4);
- /* L4 */
- clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2);
- /* L3 */
- clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV);
-
- p3 = (u32)&prcm_base->idlest_ckgen;
-
- (*f_lock_pll) (p0, p1, p2, p3);
- }
-}
-
-static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- struct dpll_per_36x_param *ptr;
-
- ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
-
- /* Moving it to the right sysclk base */
- ptr += clk_index;
-
- /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
- clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16);
- wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
-
- /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
- clrsetbits_le32(&prcm_base->clksel1_emu, 0x3F000000, ptr->m6 << 24);
-
- /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
- clrsetbits_le32(&prcm_base->clksel_cam, 0x0000003F, ptr->m5);
-
- /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
- clrsetbits_le32(&prcm_base->clksel_dss, 0x0000003F, ptr->m4);
-
- /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
- clrsetbits_le32(&prcm_base->clksel_dss, 0x00003F00, ptr->m3 << 8);
-
- /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
- clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);
-
- /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
- clrsetbits_le32(&prcm_base->clksel2_pll, 0x000FFF00, ptr->m << 8);
-
- /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
- clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n);
-
- /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
- clrsetbits_le32(&prcm_base->clksel_core, 0x00003000, ptr->m2div << 12);
-
- /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
- clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16);
- wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
-}
-
-static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
-
- /* Moving it to the right sysclk base */
- ptr = ptr + clk_index;
-
- /* PER2 DPLL (DPLL5) */
- clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_STOP);
- wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
- /* set M2 (usbtll_fck) */
- clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);
- /* set m (11-bit multiplier) */
- clrsetbits_le32(&prcm_base->clksel4_pll, 0x0007FF00, ptr->m << 8);
- /* set n (7-bit divider)*/
- clrsetbits_le32(&prcm_base->clksel4_pll, 0x0000007F, ptr->n);
- /* lock mode */
- clrsetbits_le32(&prcm_base->clken2_pll, 0x00000007, PLL_LOCK);
- wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
-}
-
-static void mpu_init_36xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
-
- /* Moving to the right sysclk */
- ptr += clk_index;
-
- /* MPU DPLL (unlocked already */
-
- /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
- clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2);
-
- /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
- clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0007FF00, ptr->m << 8);
-
- /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
- clrsetbits_le32(&prcm_base->clksel1_pll_mpu, 0x0000007F, ptr->n);
-}
-
-static void iva_init_36xx(u32 sil_index, u32 clk_index)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
-
- /* Moving to the right sysclk */
- ptr += clk_index;
-
- /* IVA DPLL */
- /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
- clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_STOP);
- wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
-
- /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
- clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2);
-
- /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
- clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0007FF00, ptr->m << 8);
-
- /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
- clrsetbits_le32(&prcm_base->clksel1_pll_iva2, 0x0000007F, ptr->n);
-
- /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
- clrsetbits_le32(&prcm_base->clken_pll_iva2, 0x00000007, PLL_LOCK);
-
- wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
-}
-
-/******************************************************************************
- * prcm_init() - inits clocks for PRCM as defined in clocks.h
- * called from SRAM, or Flash (using temp SRAM stack).
- *****************************************************************************/
-void prcm_init(void)
-{
- u32 osc_clk = 0, sys_clkin_sel;
- u32 clk_index, sil_index = 0;
- struct prm *prm_base = (struct prm *)PRM_BASE;
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-
- /*
- * Gauge the input clock speed and find out the sys_clkin_sel
- * value corresponding to the input clock.
- */
- osc_clk = get_osc_clk_speed();
- get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
-
- /* set input crystal speed */
- clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel);
-
- /* If the input clock is greater than 19.2M always divide/2 */
- if (sys_clkin_sel > 2) {
- /* input clock divider */
- clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6);
- clk_index = sys_clkin_sel / 2;
- } else {
- /* input clock divider */
- clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6);
- clk_index = sys_clkin_sel;
- }
-
- if (get_cpu_family() == CPU_OMAP36XX) {
- /*
- * In warm reset conditions on OMAP36xx/AM/DM37xx
- * the rom code incorrectly sets the DPLL4 clock
- * input divider to /6.5. Section 3.5.3.3.3.2.1 of
- * the AM/DM37x TRM explains that the /6.5 divider
- * is used only when the input clock is 13MHz.
- *
- * If the part is in this cpu family *and* the input
- * clock *is not* 13 MHz, then reset the DPLL4 clock
- * input divider to /1 as it should never set to /6.5
- * in this case.
- */
- if (sys_clkin_sel != 1) { /* 13 MHz */
- /* Bit 8: DPLL4_CLKINP_DIV */
- clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100);
- }
-
- /* Unlock MPU DPLL (slows things down, and needed later) */
- clrsetbits_le32(&prcm_base->clken_pll_mpu,
- 0x00000007, PLL_LOW_POWER_BYPASS);
- wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
- LDELAY);
-
- dpll3_init_36xx(0, clk_index);
- dpll4_init_36xx(0, clk_index);
- dpll5_init_36xx(0, clk_index);
- iva_init_36xx(0, clk_index);
- mpu_init_36xx(0, clk_index);
-
- /* Lock MPU DPLL to set frequency */
- clrsetbits_le32(&prcm_base->clken_pll_mpu,
- 0x00000007, PLL_LOCK);
- wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
- LDELAY);
- } else {
- /*
- * The DPLL tables are defined according to sysclk value and
- * silicon revision. The clk_index value will be used to get
- * the values for that input sysclk from the DPLL param table
- * and sil_index will get the values for that SysClk for the
- * appropriate silicon rev.
- */
- if (((get_cpu_family() == CPU_OMAP34XX)
- && (get_cpu_rev() >= CPU_3XX_ES20)) ||
- (get_cpu_family() == CPU_AM35XX))
- sil_index = 1;
-
- /* Unlock MPU DPLL (slows things down, and needed later) */
- clrsetbits_le32(&prcm_base->clken_pll_mpu,
- 0x00000007, PLL_LOW_POWER_BYPASS);
- wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
- LDELAY);
-
- dpll3_init_34xx(sil_index, clk_index);
- dpll4_init_34xx(sil_index, clk_index);
- dpll5_init_34xx(sil_index, clk_index);
- if (get_cpu_family() != CPU_AM35XX)
- iva_init_34xx(sil_index, clk_index);
-
- mpu_init_34xx(sil_index, clk_index);
-
- /* Lock MPU DPLL to set frequency */
- clrsetbits_le32(&prcm_base->clken_pll_mpu,
- 0x00000007, PLL_LOCK);
- wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
- LDELAY);
- }
-
- /* Set up GPTimers to sys_clk source only */
- setbits_le32(&prcm_base->clksel_per, 0x000000FF);
- setbits_le32(&prcm_base->clksel_wkup, 1);
-
- sdelay(5000);
-}
-
-/*
- * Enable usb ehci uhh, tll clocks
- */
-void ehci_clocks_enable(void)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-
- /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
- setbits_le32(&prcm_base->iclken_usbhost, 1);
- /*
- * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
- * and USBHOST_120M_FCLK (USBHOST_FCLK2)
- */
- setbits_le32(&prcm_base->fclken_usbhost, 0x00000003);
- /* Enable USBTTL_ICLK */
- setbits_le32(&prcm_base->iclken3_core, 0x00000004);
- /* Enable USBTTL_FCLK */
- setbits_le32(&prcm_base->fclken3_core, 0x00000004);
-}
-
-/******************************************************************************
- * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
- *****************************************************************************/
-void per_clocks_enable(void)
-{
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
-
- /* Enable GP2 timer. */
- setbits_le32(&prcm_base->clksel_per, 0x01); /* GPT2 = sys clk */
- setbits_le32(&prcm_base->iclken_per, 0x08); /* ICKen GPT2 */
- setbits_le32(&prcm_base->fclken_per, 0x08); /* FCKen GPT2 */
-
- /* Enable GP9 timer. */
- setbits_le32(&prcm_base->clksel_per, 0x80); /* GPT9 = 32kHz clk */
- setbits_le32(&prcm_base->iclken_per, 0x400); /* ICKen GPT9 */
- setbits_le32(&prcm_base->fclken_per, 0x400); /* FCKen GPT9 */
-
-#ifdef CONFIG_SYS_NS16550
- /* Enable UART1 clocks */
- setbits_le32(&prcm_base->fclken1_core, 0x00002000);
- setbits_le32(&prcm_base->iclken1_core, 0x00002000);
-
- /* Enable UART2 clocks */
- setbits_le32(&prcm_base->fclken1_core, 0x00004000);
- setbits_le32(&prcm_base->iclken1_core, 0x00004000);
-
- /* UART 3 Clocks */
- setbits_le32(&prcm_base->fclken_per, 0x00000800);
- setbits_le32(&prcm_base->iclken_per, 0x00000800);
-#endif
-
-#ifdef CONFIG_OMAP3_GPIO_2
- setbits_le32(&prcm_base->fclken_per, 0x00002000);
- setbits_le32(&prcm_base->iclken_per, 0x00002000);
-#endif
-#ifdef CONFIG_OMAP3_GPIO_3
- setbits_le32(&prcm_base->fclken_per, 0x00004000);
- setbits_le32(&prcm_base->iclken_per, 0x00004000);
-#endif
-#ifdef CONFIG_OMAP3_GPIO_4
- setbits_le32(&prcm_base->fclken_per, 0x00008000);
- setbits_le32(&prcm_base->iclken_per, 0x00008000);
-#endif
-#ifdef CONFIG_OMAP3_GPIO_5
- setbits_le32(&prcm_base->fclken_per, 0x00010000);
- setbits_le32(&prcm_base->iclken_per, 0x00010000);
-#endif
-#ifdef CONFIG_OMAP3_GPIO_6
- setbits_le32(&prcm_base->fclken_per, 0x00020000);
- setbits_le32(&prcm_base->iclken_per, 0x00020000);
-#endif
-
-#ifdef CONFIG_SYS_I2C_OMAP34XX
- /* Turn on all 3 I2C clocks */
- setbits_le32(&prcm_base->fclken1_core, 0x00038000);
- setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */
-#endif
- /* Enable the ICLK for 32K Sync Timer as its used in udelay */
- setbits_le32(&prcm_base->iclken_wkup, 0x00000004);
-
- if (get_cpu_family() != CPU_AM35XX)
- out_le32(&prcm_base->fclken_iva2, FCK_IVA2_ON);
-
- out_le32(&prcm_base->fclken1_core, FCK_CORE1_ON);
- out_le32(&prcm_base->iclken1_core, ICK_CORE1_ON);
- out_le32(&prcm_base->iclken2_core, ICK_CORE2_ON);
- out_le32(&prcm_base->fclken_wkup, FCK_WKUP_ON);
- out_le32(&prcm_base->iclken_wkup, ICK_WKUP_ON);
- out_le32(&prcm_base->fclken_dss, FCK_DSS_ON);
- out_le32(&prcm_base->iclken_dss, ICK_DSS_ON);
- if (get_cpu_family() != CPU_AM35XX) {
- out_le32(&prcm_base->fclken_cam, FCK_CAM_ON);
- out_le32(&prcm_base->iclken_cam, ICK_CAM_ON);
- }
-
- sdelay(1000);
-}
diff --git a/arch/arm/cpu/armv7/omap3/config.mk b/arch/arm/cpu/armv7/omap3/config.mk
deleted file mode 100644
index ad44d63840..0000000000
--- a/arch/arm/cpu/armv7/omap3/config.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Copyright 2011 Linaro Limited
-#
-# (C) Copyright 2010
-# Texas Instruments, <www.ti.com>
-#
-# Aneesh V <aneesh@ti.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-ifdef CONFIG_SPL_BUILD
-ALL-y += MLO
-else
-ALL-y += u-boot.img
-endif
diff --git a/arch/arm/cpu/armv7/omap3/emac.c b/arch/arm/cpu/armv7/omap3/emac.c
deleted file mode 100644
index 37f4b8b490..0000000000
--- a/arch/arm/cpu/armv7/omap3/emac.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- *
- * DaVinci EMAC initialization.
- *
- * (C) Copyright 2011, Ilya Yanok, Emcraft Systems
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/am35x_def.h>
-
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(bd_t *bis)
-{
- u32 reset;
-
- /* ensure that the module is out of reset */
- reset = readl(&am35x_scm_general_regs->ip_sw_reset);
- reset &= ~CPGMACSS_SW_RST;
- writel(reset, &am35x_scm_general_regs->ip_sw_reset);
-
- return davinci_emac_initialize();
-}
diff --git a/arch/arm/cpu/armv7/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c
deleted file mode 100644
index a2aadc9816..0000000000
--- a/arch/arm/cpu/armv7/omap3/emif4.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * Author :
- * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Based on mem.c and sdrc.c
- *
- * Copyright (C) 2010
- * Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/emif4.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-extern omap3_sysinfo sysinfo;
-
-static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
-
-/*
- * is_mem_sdr -
- * - Return 1 if mem type in use is SDR
- */
-u32 is_mem_sdr(void)
-{
- return 0;
-}
-
-/*
- * get_sdr_cs_size -
- * - Get size of chip select 0/1
- */
-u32 get_sdr_cs_size(u32 cs)
-{
- u32 size = 0;
-
- /* TODO: Calculate the size based on EMIF4 configuration */
- if (cs == CS0)
- size = CONFIG_SYS_CS0_SIZE;
-
- return size;
-}
-
-/*
- * get_sdr_cs_offset -
- * - Get offset of cs from cs0 start
- */
-u32 get_sdr_cs_offset(u32 cs)
-{
- u32 offset = 0;
-
- return offset;
-}
-
-/*
- * do_emif4_init -
- * - Init the emif4 module for DDR access
- * - Early init routines, called from flash or SRAM.
- */
-static void do_emif4_init(void)
-{
- unsigned int regval;
- /* Set the DDR PHY parameters in PHY ctrl registers */
- regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
- EMIF4_DDR1_EXT_STRB_DIS);
- writel(regval, &emif4_base->ddr_phyctrl1);
- writel(regval, &emif4_base->ddr_phyctrl1_shdw);
- writel(0, &emif4_base->ddr_phyctrl2);
-
- /* Reset the DDR PHY and wait till completed */
- regval = readl(&emif4_base->sdram_iodft_tlgc);
- regval |= (1<<10);
- writel(regval, &emif4_base->sdram_iodft_tlgc);
- /*Wait till that bit clears*/
- while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1);
- /*Re-verify the DDR PHY status*/
- while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
-
- regval |= (1<<0);
- writel(regval, &emif4_base->sdram_iodft_tlgc);
- /* Set SDR timing registers */
- regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
- EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
- EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
- EMIF4_TIM1_T_RP);
- writel(regval, &emif4_base->sdram_time1);
- writel(regval, &emif4_base->sdram_time1_shdw);
-
- regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
- EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
- EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
- writel(regval, &emif4_base->sdram_time2);
- writel(regval, &emif4_base->sdram_time2_shdw);
-
- regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
- writel(regval, &emif4_base->sdram_time3);
- writel(regval, &emif4_base->sdram_time3_shdw);
-
- /* Set the PWR control register */
- regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
- EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
- writel(regval, &emif4_base->sdram_pwr_mgmt);
- writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
-
- /* Set the DDR refresh rate control register */
- regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
- writel(regval, &emif4_base->sdram_refresh_ctrl);
- writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
-
- /* set the SDRAM configuration register */
- regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
- EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
- EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
- EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
- EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
- EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
- writel(regval, &emif4_base->sdram_config);
-}
-
-/*
- * dram_init -
- * - Sets uboots idea of sdram size
- */
-int dram_init(void)
-{
- unsigned int size0 = 0, size1 = 0;
-
- size0 = get_sdr_cs_size(CS0);
- /*
- * If a second bank of DDR is attached to CS1 this is
- * where it can be started. Early init code will init
- * memory on CS0.
- */
- if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
- size1 = get_sdr_cs_size(CS1);
-
- gd->ram_size = size0 + size1;
- return 0;
-}
-
-void dram_init_banksize (void)
-{
- unsigned int size0 = 0, size1 = 0;
-
- size0 = get_sdr_cs_size(CS0);
- size1 = get_sdr_cs_size(CS1);
-
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size0;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
- gd->bd->bi_dram[1].size = size1;
-}
-
-/*
- * mem_init() -
- * - Initialize memory subsystem
- */
-void mem_init(void)
-{
- do_emif4_init();
-}
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
deleted file mode 100644
index 1e587723ce..0000000000
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ /dev/null
@@ -1,476 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Initial Code by:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/clocks_omap3.h>
-#include <linux/linkage.h>
-
-/*
- * Funtion for making PPA HAL API calls in secure devices
- * Input:
- * R0 - Service ID
- * R1 - paramer list
- */
-ENTRY(do_omap3_emu_romcode_call)
- PUSH {r4-r12, lr} @ Save all registers from ROM code!
- MOV r12, r0 @ Copy the Secure Service ID in R12
- MOV r3, r1 @ Copy the pointer to va_list in R3
- MOV r1, #0 @ Process ID - 0
- MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
- @ to va_list in R3
- MOV r6, #0xFF @ Indicate new Task call
- mcr p15, 0, r0, c7, c10, 4 @ DSB
- mcr p15, 0, r0, c7, c10, 5 @ DMB
- .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
- @ because we use -march=armv5
- POP {r4-r12, pc}
-ENDPROC(do_omap3_emu_romcode_call)
-
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
-/**************************************************************************
- * cpy_clk_code: relocates clock code into SRAM where its safer to execute
- * R1 = SRAM destination address.
- *************************************************************************/
-ENTRY(cpy_clk_code)
- /* Copy DPLL code into SRAM */
- adr r0, go_to_speed /* copy from start of go_to_speed... */
- adr r2, lowlevel_init /* ... up to start of low_level_init */
-next2:
- ldmia r0!, {r3 - r10} /* copy from source address [r0] */
- stmia r1!, {r3 - r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo next2
- mov pc, lr /* back to caller */
-ENDPROC(cpy_clk_code)
-
-/* ***************************************************************************
- * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
- * -executed from SRAM.
- * R0 = CM_CLKEN_PLL-bypass value
- * R1 = CM_CLKSEL1_PLL-m, n, and divider values
- * R2 = CM_CLKSEL_CORE-divider values
- * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
- *
- * Note: If core unlocks/relocks and SDRAM is running fast already it gets
- * confused. A reset of the controller gets it back. Taking away its
- * L3 when its not in self refresh seems bad for it. Normally, this
- * code runs from flash before SDR is init so that should be ok.
- ****************************************************************************/
-ENTRY(go_to_speed)
- stmfd sp!, {r4 - r6}
-
- /* move into fast relock bypass */
- ldr r4, pll_ctl_add
- str r0, [r4]
-wait1:
- ldr r5, [r3] /* get status */
- and r5, r5, #0x1 /* isolate core status */
- cmp r5, #0x1 /* still locked? */
- beq wait1 /* if lock, loop */
-
- /* set new dpll dividers _after_ in bypass */
- ldr r5, pll_div_add1
- str r1, [r5] /* set m, n, m2 */
- ldr r5, pll_div_add2
- str r2, [r5] /* set l3/l4/.. dividers*/
- ldr r5, pll_div_add3 /* wkup */
- ldr r2, pll_div_val3 /* rsm val */
- str r2, [r5]
- ldr r5, pll_div_add4 /* gfx */
- ldr r2, pll_div_val4
- str r2, [r5]
- ldr r5, pll_div_add5 /* emu */
- ldr r2, pll_div_val5
- str r2, [r5]
-
- /* now prepare GPMC (flash) for new dpll speed */
- /* flash needs to be stable when we jump back to it */
- ldr r5, flash_cfg3_addr
- ldr r2, flash_cfg3_val
- str r2, [r5]
- ldr r5, flash_cfg4_addr
- ldr r2, flash_cfg4_val
- str r2, [r5]
- ldr r5, flash_cfg5_addr
- ldr r2, flash_cfg5_val
- str r2, [r5]
- ldr r5, flash_cfg1_addr
- ldr r2, [r5]
- orr r2, r2, #0x3 /* up gpmc divider */
- str r2, [r5]
-
- /* lock DPLL3 and wait a bit */
- orr r0, r0, #0x7 /* set up for lock mode */
- str r0, [r4] /* lock */
- nop /* ARM slow at this point working at sys_clk */
- nop
- nop
- nop
-wait2:
- ldr r5, [r3] /* get status */
- and r5, r5, #0x1 /* isolate core status */
- cmp r5, #0x1 /* still locked? */
- bne wait2 /* if lock, loop */
- nop
- nop
- nop
- nop
- ldmfd sp!, {r4 - r6}
- mov pc, lr /* back to caller, locked */
-ENDPROC(go_to_speed)
-
-_go_to_speed: .word go_to_speed
-
-/* these constants need to be close for PIC code */
-/* The Nor has to be in the Flash Base CS0 for this condition to happen */
-flash_cfg1_addr:
- .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
-flash_cfg3_addr:
- .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
-flash_cfg3_val:
- .word STNOR_GPMC_CONFIG3
-flash_cfg4_addr:
- .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
-flash_cfg4_val:
- .word STNOR_GPMC_CONFIG4
-flash_cfg5_val:
- .word STNOR_GPMC_CONFIG5
-flash_cfg5_addr:
- .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
-pll_ctl_add:
- .word CM_CLKEN_PLL
-pll_div_add1:
- .word CM_CLKSEL1_PLL
-pll_div_add2:
- .word CM_CLKSEL_CORE
-pll_div_add3:
- .word CM_CLKSEL_WKUP
-pll_div_val3:
- .word (WKUP_RSM << 1)
-pll_div_add4:
- .word CM_CLKSEL_GFX
-pll_div_val4:
- .word (GFX_DIV << 0)
-pll_div_add5:
- .word CM_CLKSEL1_EMU
-pll_div_val5:
- .word CLSEL1_EMU_VAL
-
-#endif
-
-ENTRY(lowlevel_init)
- ldr sp, SRAM_STACK
- str ip, [sp] /* stash ip register */
- mov ip, lr /* save link reg across call */
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
-/*
- * No need to copy/exec the clock code - DPLL adjust already done
- * in NAND/oneNAND Boot.
- */
- ldr r1, =SRAM_CLK_CODE
- bl cpy_clk_code
-#endif /* NAND Boot */
- mov lr, ip /* restore link reg */
- ldr ip, [sp] /* restore save ip */
- /* tail-call s_init to setup pll, mux, memory */
- b s_init
-
-ENDPROC(lowlevel_init)
-
- /* the literal pools origin */
- .ltorg
-
-REG_CONTROL_STATUS:
- .word CONTROL_STATUS
-SRAM_STACK:
- .word LOW_LEVEL_SRAM_STACK
-
-/* DPLL(1-4) PARAM TABLES */
-
-/*
- * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
- * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
- * The values are defined for all possible sysclk and for ES1 and ES2.
- */
-
-mpu_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
-/* ES2 */
-.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
-/* 3410 */
-.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
-
-/* 13MHz */
-/* ES1 */
-.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
-/* ES2 */
-.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
-/* 3410 */
-.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
-
-/* 19.2MHz */
-/* ES1 */
-.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
-/* ES2 */
-.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
-/* 3410 */
-.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
-
-/* 26MHz */
-/* ES1 */
-.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
-/* ES2 */
-.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
-/* 3410 */
-.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
-
-/* 38.4MHz */
-/* ES1 */
-.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
-/* ES2 */
-.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
-/* 3410 */
-.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
-
-
-.globl get_mpu_dpll_param
-get_mpu_dpll_param:
- adr r0, mpu_dpll_param
- mov pc, lr
-
-iva_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
-/* ES2 */
-.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
-/* 3410 */
-.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
-
-/* 13MHz */
-/* ES1 */
-.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
-/* ES2 */
-.word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
-/* 3410 */
-.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
-
-/* 19.2MHz */
-/* ES1 */
-.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
-/* ES2 */
-.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
-/* 3410 */
-.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
-
-/* 26MHz */
-/* ES1 */
-.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
-/* ES2 */
-.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
-/* 3410 */
-.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
-
-/* 38.4MHz */
-/* ES1 */
-.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
-/* ES2 */
-.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
-/* 3410 */
-.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
-
-
-.globl get_iva_dpll_param
-get_iva_dpll_param:
- adr r0, iva_dpll_param
- mov pc, lr
-
-/* Core DPLL targets for L3 at 166 & L133 */
-core_dpll_param:
-/* 12MHz */
-/* ES1 */
-.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
-/* ES2 */
-.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
-/* 3410 */
-.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
-
-/* 13MHz */
-/* ES1 */
-.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
-/* ES2 */
-.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
-/* 3410 */
-.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
-
-/* 19.2MHz */
-/* ES1 */
-.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
-/* ES2 */
-.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
-/* 3410 */
-.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
-
-/* 26MHz */
-/* ES1 */
-.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
-/* ES2 */
-.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
-/* 3410 */
-.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
-
-/* 38.4MHz */
-/* ES1 */
-.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
-/* ES2 */
-.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
-/* 3410 */
-.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
-
-.globl get_core_dpll_param
-get_core_dpll_param:
- adr r0, core_dpll_param
- mov pc, lr
-
-/* PER DPLL values are same for both ES1 and ES2 */
-per_dpll_param:
-/* 12MHz */
-.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
-
-/* 13MHz */
-.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
-
-/* 19.2MHz */
-.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
-
-/* 26MHz */
-.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
-
-/* 38.4MHz */
-.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
-
-.globl get_per_dpll_param
-get_per_dpll_param:
- adr r0, per_dpll_param
- mov pc, lr
-
-/* PER2 DPLL values */
-per2_dpll_param:
-/* 12MHz */
-.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
-
-/* 13MHz */
-.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
-
-/* 19.2MHz */
-.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
-
-/* 26MHz */
-.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
-
-/* 38.4MHz */
-.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
-
-.globl get_per2_dpll_param
-get_per2_dpll_param:
- adr r0, per2_dpll_param
- mov pc, lr
-
-/*
- * Tables for 36XX/37XX devices
- *
- */
-mpu_36x_dpll_param:
-/* 12MHz */
-.word 50, 0, 0, 1
-/* 13MHz */
-.word 600, 12, 0, 1
-/* 19.2MHz */
-.word 125, 3, 0, 1
-/* 26MHz */
-.word 300, 12, 0, 1
-/* 38.4MHz */
-.word 125, 7, 0, 1
-
-iva_36x_dpll_param:
-/* 12MHz */
-.word 130, 2, 0, 1
-/* 13MHz */
-.word 20, 0, 0, 1
-/* 19.2MHz */
-.word 325, 11, 0, 1
-/* 26MHz */
-.word 10, 0, 0, 1
-/* 38.4MHz */
-.word 325, 23, 0, 1
-
-core_36x_dpll_param:
-/* 12MHz */
-.word 100, 2, 0, 1
-/* 13MHz */
-.word 400, 12, 0, 1
-/* 19.2MHz */
-.word 375, 17, 0, 1
-/* 26MHz */
-.word 200, 12, 0, 1
-/* 38.4MHz */
-.word 375, 35, 0, 1
-
-per_36x_dpll_param:
-/* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
-.word 12000, 360, 4, 9, 16, 5, 4, 3, 1
-.word 13000, 864, 12, 9, 16, 9, 4, 3, 1
-.word 19200, 360, 7, 9, 16, 5, 4, 3, 1
-.word 26000, 432, 12, 9, 16, 9, 4, 3, 1
-.word 38400, 360, 15, 9, 16, 5, 4, 3, 1
-
-per2_36x_dpll_param:
-/* 12MHz */
-.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
-/* 13MHz */
-.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
-/* 19.2MHz */
-.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
-/* 26MHz */
-.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
-/* 38.4MHz */
-.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
-
-
-ENTRY(get_36x_mpu_dpll_param)
- adr r0, mpu_36x_dpll_param
- mov pc, lr
-ENDPROC(get_36x_mpu_dpll_param)
-
-ENTRY(get_36x_iva_dpll_param)
- adr r0, iva_36x_dpll_param
- mov pc, lr
-ENDPROC(get_36x_iva_dpll_param)
-
-ENTRY(get_36x_core_dpll_param)
- adr r0, core_36x_dpll_param
- mov pc, lr
-ENDPROC(get_36x_core_dpll_param)
-
-ENTRY(get_36x_per_dpll_param)
- adr r0, per_36x_dpll_param
- mov pc, lr
-ENDPROC(get_36x_per_dpll_param)
-
-ENTRY(get_36x_per2_dpll_param)
- adr r0, per2_36x_dpll_param
- mov pc, lr
-ENDPROC(get_36x_per2_dpll_param)
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
deleted file mode 100644
index 4f15ac9cb5..0000000000
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * Functions related to OMAP3 SDRC.
- *
- * This file has been created after exctracting and consolidating
- * the SDRC related content from mem.c and board.c, also created
- * generic init function (mem_init).
- *
- * Copyright (C) 2004-2010
- * Texas Instruments Incorporated - http://www.ti.com/
- *
- * Copyright (C) 2011
- * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
- *
- * Author :
- * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * Original implementation by (mem.c, board.c) :
- * Sunil Kumar <sunilsaini05@gmail.com>
- * Shashi Ranjan <shashiranjanmca05@gmail.com>
- * Manikandan Pillai <mani.pillai@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-extern omap3_sysinfo sysinfo;
-
-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
-
-/*
- * is_mem_sdr -
- * - Return 1 if mem type in use is SDR
- */
-u32 is_mem_sdr(void)
-{
- if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
- return 1;
- return 0;
-}
-
-/*
- * make_cs1_contiguous -
- * - When we have CS1 populated we want to have it mapped after cs0 to allow
- * command line mem=xyz use all memory with out discontinuous support
- * compiled in. We could do it in the ATAG, but there really is two banks...
- */
-void make_cs1_contiguous(void)
-{
- u32 size, a_add_low, a_add_high;
-
- size = get_sdr_cs_size(CS0);
- size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
- a_add_high = (size & 3) << 8; /* set up low field */
- a_add_low = (size & 0x3C) >> 2; /* set up high field */
- writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
-
-}
-
-
-/*
- * get_sdr_cs_size -
- * - Get size of chip select 0/1
- */
-u32 get_sdr_cs_size(u32 cs)
-{
- u32 size;
-
- /* get ram size field */
- size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
- size &= 0x3FF; /* remove unwanted bits */
- size <<= 21; /* multiply by 2 MiB to find size in MB */
- return size;
-}
-
-/*
- * get_sdr_cs_offset -
- * - Get offset of cs from cs0 start
- */
-u32 get_sdr_cs_offset(u32 cs)
-{
- u32 offset;
-
- if (!cs)
- return 0;
-
- offset = readl(&sdrc_base->cs_cfg);
- offset = (offset & 15) << 27 | (offset & 0x300) << 17;
-
- return offset;
-}
-
-/*
- * write_sdrc_timings -
- * - Takes CS and associated timings and initalize SDRAM
- * - Test CS to make sure it's OK for use
- */
-static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
- struct board_sdrc_timings *timings)
-{
- /* Setup timings we got from the board. */
- writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
- writel(timings->ctrla, &sdrc_actim_base->ctrla);
- writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
- writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
- writel(CMD_NOP, &sdrc_base->cs[cs].manual);
- writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
- writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
- writel(timings->mr, &sdrc_base->cs[cs].mr);
-
- /*
- * Test ram in this bank
- * Disable if bad or not present
- */
- if (!mem_ok(cs))
- writel(0, &sdrc_base->cs[cs].mcfg);
-}
-
-/*
- * do_sdrc_init -
- * - Code called once in C-Stack only context for CS0 and with early being
- * true and a possible 2nd time depending on memory configuration from
- * stack+global context.
- */
-void do_sdrc_init(u32 cs, u32 early)
-{
- struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
- struct board_sdrc_timings timings;
-
- sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
- sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
-
- /* set some default timings */
- timings.sharing = SDRC_SHARING;
-
- /*
- * When called in the early context this may be SPL and we will
- * need to set all of the timings. This ends up being board
- * specific so we call a helper function to take care of this
- * for us. Otherwise, to be safe, we need to copy the settings
- * from the first bank to the second. We will setup CS0,
- * then set cs_cfg to the appropriate value then try and
- * setup CS1.
- */
-#ifdef CONFIG_SPL_BUILD
- /* set/modify board-specific timings */
- get_board_mem_timings(&timings);
-#endif
- if (early) {
- /* reset sdrc controller */
- writel(SOFTRESET, &sdrc_base->sysconfig);
- wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
- 12000000);
- writel(0, &sdrc_base->sysconfig);
-
- /* setup sdrc to ball mux */
- writel(timings.sharing, &sdrc_base->sharing);
-
- /* Disable Power Down of CKE because of 1 CKE on combo part */
- writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
- &sdrc_base->power);
-
- writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
- sdelay(0x20000);
-#ifdef CONFIG_SPL_BUILD
- write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
- make_cs1_contiguous();
- write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
-#endif
-
- }
-
- /*
- * If we aren't using SPL we have been loaded by some
- * other means which may not have correctly initialized
- * both CS0 and CS1 (such as some older versions of x-loader)
- * so we may be asked now to setup CS1.
- */
- if (cs == CS1) {
- timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),
- timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
- timings.ctrla = readl(&sdrc_actim_base0->ctrla);
- timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);
- timings.mr = readl(&sdrc_base->cs[CS0].mr);
- write_sdrc_timings(cs, sdrc_actim_base1, &timings);
- }
-}
-
-/*
- * dram_init -
- * - Sets uboots idea of sdram size
- */
-int dram_init(void)
-{
- unsigned int size0 = 0, size1 = 0;
-
- size0 = get_sdr_cs_size(CS0);
- /*
- * We always need to have cs_cfg point at where the second
- * bank would be, if present. Failure to do so can lead to
- * strange situations where memory isn't detected and
- * configured correctly. CS0 will already have been setup
- * at this point.
- */
- make_cs1_contiguous();
- do_sdrc_init(CS1, NOT_EARLY);
- size1 = get_sdr_cs_size(CS1);
-
- gd->ram_size = size0 + size1;
-
- return 0;
-}
-
-void dram_init_banksize (void)
-{
- unsigned int size0 = 0, size1 = 0;
-
- size0 = get_sdr_cs_size(CS0);
- size1 = get_sdr_cs_size(CS1);
-
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = size0;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
- gd->bd->bi_dram[1].size = size1;
-}
-
-/*
- * mem_init -
- * - Init the sdrc chip,
- * - Selects CS0 and CS1,
- */
-void mem_init(void)
-{
- /* only init up first bank here */
- do_sdrc_init(CS0, EARLY_INIT);
-}
diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/cpu/armv7/omap3/spl_id_nand.c
deleted file mode 100644
index 0e2f0a2f6d..0000000000
--- a/arch/arm/cpu/armv7/omap3/spl_id_nand.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2011
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Tom Rini <trini@ti.com>
- *
- * Initial Code from:
- * Richard Woodruff <r-woodruff2@ti.com>
- * Jian Zhang <jzhang@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <jffs2/load_kernel.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/omap_gpmc.h>
-#include <asm/io.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mem.h>
-
-/*
- * Many boards will want to know the results of the NAND_CMD_READID command
- * in order to decide what to do about DDR initialization. This function
- * allows us to do that very early and to pass those results back to the
- * board so it can make whatever decisions need to be made.
- */
-int identify_nand_chip(int *mfr, int *id)
-{
- int loops = 1000;
-
- /* Make sure that we have setup GPMC for NAND correctly. */
- set_gpmc_cs0(MTD_DEV_TYPE_NAND);
-
- sdelay(2000);
-
- /* Issue a RESET and then READID */
- writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
- writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
- while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
- != NAND_STATUS_READY) {
- sdelay(100);
- if (--loops == 0)
- return 1;
- }
- writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd);
-
- /* Set the address to read to 0x0 */
- writeb(0x0, &gpmc_cfg->cs[0].nand_adr);
-
- /* Read off the manufacturer and device id. */
- *mfr = readb(&gpmc_cfg->cs[0].nand_dat);
- *id = readb(&gpmc_cfg->cs[0].nand_dat);
-
- return 0;
-}
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
deleted file mode 100644
index 6818fab253..0000000000
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ /dev/null
@@ -1,343 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Author :
- * Manikandan Pillai <mani.pillai@ti.com>
- *
- * Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mem.h> /* get mem tables */
-#include <asm/arch/sys_proto.h>
-#include <asm/bootm.h>
-
-#include <i2c.h>
-#include <linux/compiler.h>
-
-extern omap3_sysinfo sysinfo;
-static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-static char *rev_s[CPU_3XX_MAX_REV] = {
- "1.0",
- "2.0",
- "2.1",
- "3.0",
- "3.1",
- "UNKNOWN",
- "UNKNOWN",
- "3.1.2"};
-
-/* this is the revision table for 37xx CPUs */
-static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
- "1.0",
- "1.1",
- "1.2"};
-#endif /* CONFIG_DISPLAY_CPUINFO */
-
-void omap_die_id(unsigned int *die_id)
-{
- struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
-
- die_id[0] = readl(&id_base->die_id_0);
- die_id[1] = readl(&id_base->die_id_1);
- die_id[2] = readl(&id_base->die_id_2);
- die_id[3] = readl(&id_base->die_id_3);
-}
-
-/******************************************
- * get_cpu_type(void) - extract cpu info
- ******************************************/
-u32 get_cpu_type(void)
-{
- return readl(&ctrl_base->ctrl_omap_stat);
-}
-
-/******************************************
- * get_cpu_id(void) - extract cpu id
- * returns 0 for ES1.0, cpuid otherwise
- ******************************************/
-u32 get_cpu_id(void)
-{
- struct ctrl_id *id_base;
- u32 cpuid = 0;
-
- /*
- * On ES1.0 the IDCODE register is not exposed on L4
- * so using CPU ID to differentiate between ES1.0 and > ES1.0.
- */
- __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
- if ((cpuid & 0xf) == 0x0) {
- return 0;
- } else {
- /* Decode the IDs on > ES1.0 */
- id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
-
- cpuid = readl(&id_base->idcode);
- }
-
- return cpuid;
-}
-
-/******************************************
- * get_cpu_family(void) - extract cpu info
- ******************************************/
-u32 get_cpu_family(void)
-{
- u16 hawkeye;
- u32 cpu_family;
- u32 cpuid = get_cpu_id();
-
- if (cpuid == 0)
- return CPU_OMAP34XX;
-
- hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
- switch (hawkeye) {
- case HAWKEYE_OMAP34XX:
- cpu_family = CPU_OMAP34XX;
- break;
- case HAWKEYE_AM35XX:
- cpu_family = CPU_AM35XX;
- break;
- case HAWKEYE_OMAP36XX:
- cpu_family = CPU_OMAP36XX;
- break;
- default:
- cpu_family = CPU_OMAP34XX;
- }
-
- return cpu_family;
-}
-
-/******************************************
- * get_cpu_rev(void) - extract version info
- ******************************************/
-u32 get_cpu_rev(void)
-{
- u32 cpuid = get_cpu_id();
-
- if (cpuid == 0)
- return CPU_3XX_ES10;
- else
- return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
-}
-
-/*****************************************************************
- * get_sku_id(void) - read sku_id to get info on max clock rate
- *****************************************************************/
-u32 get_sku_id(void)
-{
- struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
- return readl(&id_base->sku_id) & SKUID_CLK_MASK;
-}
-
-/***************************************************************************
- * get_gpmc0_base() - Return current address hardware will be
- * fetching from. The below effectively gives what is correct, its a bit
- * mis-leading compared to the TRM. For the most general case the mask
- * needs to be also taken into account this does work in practice.
- * - for u-boot we currently map:
- * -- 0 to nothing,
- * -- 4 to flash
- * -- 8 to enent
- * -- c to wifi
- ****************************************************************************/
-u32 get_gpmc0_base(void)
-{
- u32 b;
-
- b = readl(&gpmc_cfg->cs[0].config7);
- b &= 0x1F; /* keep base [5:0] */
- b = b << 24; /* ret 0x0b000000 */
- return b;
-}
-
-/*******************************************************************
- * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
- *******************************************************************/
-u32 get_gpmc0_width(void)
-{
- return WIDTH_16BIT;
-}
-
-/*************************************************************************
- * get_board_rev() - setup to pass kernel board revision information
- * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
- *************************************************************************/
-#ifdef CONFIG_REVISION_TAG
-u32 __weak get_board_rev(void)
-{
- return 0x20;
-}
-#endif
-
-/********************************************************
- * get_base(); get upper addr of current execution
- *******************************************************/
-static u32 get_base(void)
-{
- u32 val;
-
- __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
- val &= 0xF0000000;
- val >>= 28;
- return val;
-}
-
-/********************************************************
- * is_running_in_flash() - tell if currently running in
- * FLASH.
- *******************************************************/
-u32 is_running_in_flash(void)
-{
- if (get_base() < 4)
- return 1; /* in FLASH */
-
- return 0; /* running in SRAM or SDRAM */
-}
-
-/********************************************************
- * is_running_in_sram() - tell if currently running in
- * SRAM.
- *******************************************************/
-u32 is_running_in_sram(void)
-{
- if (get_base() == 4)
- return 1; /* in SRAM */
-
- return 0; /* running in FLASH or SDRAM */
-}
-
-/********************************************************
- * is_running_in_sdram() - tell if currently running in
- * SDRAM.
- *******************************************************/
-u32 is_running_in_sdram(void)
-{
- if (get_base() > 4)
- return 1; /* in SDRAM */
-
- return 0; /* running in SRAM or FLASH */
-}
-
-/***************************************************************
- * get_boot_type() - Is this an XIP type device or a stream one
- * bits 4-0 specify type. Bit 5 says mem/perif
- ***************************************************************/
-u32 get_boot_type(void)
-{
- return (readl(&ctrl_base->status) & SYSBOOT_MASK);
-}
-
-/*************************************************************
- * get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
- return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
-}
-
-#ifdef CONFIG_DISPLAY_CPUINFO
-/**
- * Print CPU information
- */
-int print_cpuinfo (void)
-{
- char *cpu_family_s, *cpu_s, *sec_s, *max_clk;
-
- switch (get_cpu_family()) {
- case CPU_OMAP34XX:
- cpu_family_s = "OMAP";
- switch (get_cpu_type()) {
- case OMAP3503:
- cpu_s = "3503";
- break;
- case OMAP3515:
- cpu_s = "3515";
- break;
- case OMAP3525:
- cpu_s = "3525";
- break;
- case OMAP3530:
- cpu_s = "3530";
- break;
- default:
- cpu_s = "35XX";
- break;
- }
- if ((get_cpu_rev() >= CPU_3XX_ES31) &&
- (get_sku_id() == SKUID_CLK_720MHZ))
- max_clk = "720 MHz";
- else
- max_clk = "600 MHz";
-
- break;
- case CPU_AM35XX:
- cpu_family_s = "AM";
- switch (get_cpu_type()) {
- case AM3505:
- cpu_s = "3505";
- break;
- case AM3517:
- cpu_s = "3517";
- break;
- default:
- cpu_s = "35XX";
- break;
- }
- max_clk = "600 Mhz";
- break;
- case CPU_OMAP36XX:
- cpu_family_s = "OMAP";
- switch (get_cpu_type()) {
- case OMAP3730:
- cpu_s = "3630/3730";
- break;
- default:
- cpu_s = "36XX/37XX";
- break;
- }
- max_clk = "1 Ghz";
- break;
- default:
- cpu_family_s = "OMAP";
- cpu_s = "35XX";
- max_clk = "600 Mhz";
- }
-
- switch (get_device_type()) {
- case TST_DEVICE:
- sec_s = "TST";
- break;
- case EMU_DEVICE:
- sec_s = "EMU";
- break;
- case HS_DEVICE:
- sec_s = "HS";
- break;
- case GP_DEVICE:
- sec_s = "GP";
- break;
- default:
- sec_s = "?";
- }
-
- if (CPU_OMAP36XX == get_cpu_family())
- printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n",
- cpu_family_s, cpu_s, sec_s,
- rev_s_37xx[get_cpu_rev()], max_clk);
- else
- printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
- cpu_family_s, cpu_s, sec_s,
- rev_s[get_cpu_rev()], max_clk);
-
- return 0;
-}
-#endif /* CONFIG_DISPLAY_CPUINFO */
generated by cgit (git 2.34.1) at 2024-12-28 13:25:10 +0000