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authorNishanth Menon <nm@ti.com>2015-03-09 17:12:03 -0500
committerTom Rini <trini@konsulko.com>2015-03-13 09:28:55 -0400
commit6d8abe6a8a5981685687a0f2fd660e034d974824 (patch)
tree374b51e0afea70f54fecf878efb89715da66d279 /arch/arm/cpu/armv7/omap4/hwinit.c
parent9b4d65f918dd84a479552b86ef2cde389926738f (diff)
ARM: OMAP: Change set_pl310_ctrl_reg to be generic
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function. So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation. While at this, smc #0 is maintained as handcoded assembly thanks to various gcc version eccentricities, discussion thread: http://marc.info/?t=142542166800001&r=1&w=2 Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap4/hwinit.c')
-rw-r--r--arch/arm/cpu/armv7/omap4/hwinit.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c
index db16548fac..9792761d40 100644
--- a/arch/arm/cpu/armv7/omap4/hwinit.c
+++ b/arch/arm/cpu/armv7/omap4/hwinit.c
@@ -159,11 +159,11 @@ void init_omap_revision(void)
#ifndef CONFIG_SYS_L2CACHE_OFF
void v7_outer_cache_enable(void)
{
- set_pl310_ctrl_reg(1);
+ omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
}
void v7_outer_cache_disable(void)
{
- set_pl310_ctrl_reg(0);
+ omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */