diff options
| author | Nishanth Menon <nm@ti.com> | 2013-05-30 03:19:31 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-06-10 08:43:10 -0400 |
| commit | 18c9d55ac611784d161440bb9f127e372e132856 (patch) | |
| tree | 85e31364c96bdd69d1d582cf05d8b29da0d6cd84 /arch/arm/cpu/armv7/omap5/hw_data.c | |
| parent | 3332b244214d63dcf347fefb700fd71becb4b46e (diff) | |
ARM: OMAP5: DRA7xx: support class 0 optimized voltages
DRA752 now uses AVS Class 0 voltages which are voltages in efuse.
This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.
This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5/hw_data.c')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 90274a02cf..bddcaed179 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -338,22 +338,32 @@ struct vcores_data omap5430_volts_es2 = { struct vcores_data dra752_volts = { .mpu.value = VDD_MPU_DRA752, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU, .mpu.pmic = &tps659038, .eve.value = VDD_EVE_DRA752, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE, .eve.pmic = &tps659038, .gpu.value = VDD_GPU_DRA752, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU, .gpu.pmic = &tps659038, .core.value = VDD_CORE_DRA752, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, .core.addr = TPS659038_REG_ADDR_SMPS7_CORE, .core.pmic = &tps659038, .iva.value = VDD_IVA_DRA752, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA, .iva.pmic = &tps659038, }; |