diff options
| author | Kishon Vijay Abraham I <kishon@ti.com> | 2015-08-19 16:16:25 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-08-28 12:33:21 -0400 |
| commit | ca5a0f172ebd907cfc21fe7c8744b0b1752bc66f (patch) | |
| tree | e4d8e8e126372c32300a5115aff19c108be0a714 /arch/arm/cpu/armv7/omap5/hw_data.c | |
| parent | 7ba792c04481c02b994260c7d12bd9ecdf6b6d0e (diff) | |
ARM: OMAP5: Add functions to enable and disable USB clocks
Added functions to enable and disable USB clocks which can be invoked
during USB init and USB exit respectively.
Cc: Roger Quadros <rogerq@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5/hw_data.c')
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 97 |
1 files changed, 97 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index e0ee23f3d1..bec6539ef5 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -622,6 +622,103 @@ void disable_edma3_clocks(void) } #endif +#ifdef CONFIG_USB_DWC3 +void enable_usb_clocks(int index) +{ + u32 cm_l3init_usb_otg_ss_clkctrl = 0; + + if (index == 0) { + cm_l3init_usb_otg_ss_clkctrl = + (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; + /* Enable 960 MHz clock for dwc3 */ + setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, + OPTFCLKEN_REFCLK960M); + + /* Enable 32 KHz clock for dwc3 */ + setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + } else if (index == 1) { + cm_l3init_usb_otg_ss_clkctrl = + (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; + /* Enable 960 MHz clock for dwc3 */ + setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, + OPTFCLKEN_REFCLK960M); + + /* Enable 32 KHz clock for dwc3 */ + setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + + /* Enable 60 MHz clock for USB2PHY2 */ + setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, + L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); + } + + u32 const clk_domains_usb[] = { + 0 + }; + + u32 const clk_modules_hw_auto_usb[] = { + (*prcm)->cm_l3init_ocp2scp1_clkctrl, + cm_l3init_usb_otg_ss_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_usb[] = { + 0 + }; + + do_enable_clocks(clk_domains_usb, + clk_modules_hw_auto_usb, + clk_modules_explicit_en_usb, + 1); +} + +void disable_usb_clocks(int index) +{ + u32 cm_l3init_usb_otg_ss_clkctrl = 0; + + if (index == 0) { + cm_l3init_usb_otg_ss_clkctrl = + (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; + /* Disable 960 MHz clock for dwc3 */ + clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, + OPTFCLKEN_REFCLK960M); + + /* Disable 32 KHz clock for dwc3 */ + clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + } else if (index == 1) { + cm_l3init_usb_otg_ss_clkctrl = + (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; + /* Disable 960 MHz clock for dwc3 */ + clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, + OPTFCLKEN_REFCLK960M); + + /* Disable 32 KHz clock for dwc3 */ + clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + + /* Disable 60 MHz clock for USB2PHY2 */ + clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, + L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); + } + + u32 const clk_domains_usb[] = { + 0 + }; + + u32 const clk_modules_disable[] = { + (*prcm)->cm_l3init_ocp2scp1_clkctrl, + cm_l3init_usb_otg_ss_clkctrl, + 0 + }; + + do_disable_clocks(clk_domains_usb, + clk_modules_disable, + 1); +} +#endif + const struct ctrl_ioregs ioregs_omap5430 = { .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, |