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authorLokesh Vutla <lokeshvutla@ti.com>2013-02-17 23:33:37 +0000
committerTom Rini <trini@ti.com>2013-03-11 11:06:11 -0400
commitd4e4129c31cf571824a1b34aa0b9210c876be718 (patch)
tree24bcc9f3d42eafdac0786f7f10075398f06acc61 /arch/arm/cpu/armv7/omap5/hw_data.c
parentd4d986ee27fe6a78e50d4789d5b08b87a5e64892 (diff)
arm: dra7xx: clock: Add the prcm changes
PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX. So adding the necessary register changes for DRA7XX socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap5/hw_data.c')
-rw-r--r--arch/arm/cpu/armv7/omap5/hw_data.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index faf5effd73..9b6b2dbe47 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -278,7 +278,7 @@ void enable_basic_clocks(void)
};
u32 const clk_modules_hw_auto_essential[] = {
- (*prcm)->cm_l3_2_gpmc_clkctrl,
+ (*prcm)->cm_l3_gpmc_clkctrl,
(*prcm)->cm_memif_emif_1_clkctrl,
(*prcm)->cm_memif_emif_2_clkctrl,
(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
@@ -503,6 +503,10 @@ void hw_data_init(void)
*omap_vcores = &omap5430_volts_es2;
break;
+ case DRA752_ES1_0:
+ *prcm = &dra7xx_prcm;
+ break;
+
default:
printf("\n INVALID OMAP REVISION ");
}