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author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-05-05 10:09:06 +0200 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-05-05 10:09:06 +0200 |
commit | b939689c7b87773c44275a578ffc8674a867e39d (patch) | |
tree | 785d71eb0bbc707385e4456a14b21706223d99a3 /arch/arm/cpu/armv7/socfpga/reset_manager.c | |
parent | 97840b5d1fe0960134c3553a9d9d1c1cd1be784d (diff) | |
parent | ace97d26176a3ebc9ec07738450de93eea35975c (diff) |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/cpu/armv7/socfpga/reset_manager.c')
-rw-r--r-- | arch/arm/cpu/armv7/socfpga/reset_manager.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c index 25921e76c4..45b352bdfc 100644 --- a/arch/arm/cpu/armv7/socfpga/reset_manager.c +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -113,3 +113,27 @@ void socfpga_spim_enable(void) clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) | (1 << RSTMGR_PERMODRST_SPIM1_LSB)); } + +/* Bring UART0 out of reset. */ +void socfpga_uart0_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_UART0_LSB); +} + +/* Bring SDRAM controller out of reset. */ +void socfpga_sdram_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SDR_LSB); +} + +/* Bring OSC1 timer out of reset. */ +void socfpga_osc1timer_enable(void) +{ + const void *reset = &reset_manager_base->per_mod_reset; + + clrbits_le32(reset, 1 << RSTMGR_PERMODRST_OSC1TIMER0_LSB); +} |