arm: socfpga: fpga: Add SoCFPGA FPGA programming interface

Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

V2: Move the not-CPU specific stuff into drivers/fpga/ and base
    this on the cleaned up altera FPGA support.

3 files changed, 116 insertions, 1 deletions

diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
index eb33f2c5fb..8b6e108c42 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -8,5 +8,6 @@
 #
 
 obj-y	:= lowlevel_init.o
-obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o
+obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
+	   fpga_manager.o
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/fpga_manager.c b/arch/arm/cpu/armv7/socfpga/fpga_manager.c
new file mode 100644
index 0000000000..43fd2fedee
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/fpga_manager.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * This file contains only support functions used also by the SoCFPGA
+ * platform code, the real meat is located in drivers/fpga/socfpga.c .
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timeout count */
+#define FPGA_TIMEOUT_CNT		0x1000000
+
+static struct socfpga_fpga_manager *fpgamgr_regs =
+	(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+
+/* Check whether FPGA Init_Done signal is high */
+static int is_fpgamgr_initdone_high(void)
+{
+	unsigned long val;
+
+	val = readl(&fpgamgr_regs->gpio_ext_porta);
+	return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
+}
+
+/* Get the FPGA mode */
+int fpgamgr_get_mode(void)
+{
+	unsigned long val;
+
+	val = readl(&fpgamgr_regs->stat);
+	return val & FPGAMGRREGS_STAT_MODE_MASK;
+}
+
+/* Check whether FPGA is ready to be accessed */
+int fpgamgr_test_fpga_ready(void)
+{
+	/* Check for init done signal */
+	if (!is_fpgamgr_initdone_high())
+		return 0;
+
+	/* Check again to avoid false glitches */
+	if (!is_fpgamgr_initdone_high())
+		return 0;
+
+	if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
+		return 0;
+
+	return 1;
+}
+
+/* Poll until FPGA is ready to be accessed or timeout occurred */
+int fpgamgr_poll_fpga_ready(void)
+{
+	unsigned long i;
+
+	/* If FPGA is blank, wait till WD invoke warm reset */
+	for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+		/* check for init done signal */
+		if (!is_fpgamgr_initdone_high())
+			continue;
+		/* check again to avoid false glitches */
+		if (!is_fpgamgr_initdone_high())
+			continue;
+		return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index f41c329a43..b07d97ee05 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <altera.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/reset_manager.h>
@@ -93,6 +94,39 @@ int overwrite_console(void)
 }
 #endif
 
+#ifdef CONFIG_FPGA
+/*
+ * FPGA programming support for SoC FPGA Cyclone V
+ */
+static Altera_desc altera_fpga[] = {
+	{
+		/* Family */
+		Altera_SoCFPGA,
+		/* Interface type */
+		fast_passive_parallel,
+		/* No limitation as additional data will be ignored */
+		-1,
+		/* No device function table */
+		NULL,
+		/* Base interface address specified in driver */
+		NULL,
+		/* No cookie implementation */
+		0
+	},
+};
+
+/* add device descriptor to FPGA device table */
+static void socfpga_fpga_add(void)
+{
+	int i;
+	fpga_init();
+	for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
+		fpga_add(fpga_altera, &altera_fpga[i]);
+}
+#else
+static inline void socfpga_fpga_add(void) {}
+#endif
+
 int arch_cpu_init(void)
 {
 	/*
@@ -108,5 +142,7 @@ int arch_cpu_init(void)
 
 int misc_init_r(void)
 {
+	/* Add device descriptor to FPGA device table */
+	socfpga_fpga_add();
 	return 0;
 }