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author | Siarhei Siamashka <siarhei.siamashka@gmail.com> | 2014-08-03 05:32:52 +0300 |
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committer | Hans de Goede <hdegoede@redhat.com> | 2014-08-12 08:42:33 +0200 |
commit | b5c71f5f9c1634d72f40b2c17aeff53ef8fdf8e0 (patch) | |
tree | 9eb97306507bacbd8913b17d6df96091f12353c5 /arch/arm/cpu/armv7/sunxi/board.c | |
parent | d755a5fb20a7e3192d301d6d6a44814b10fb4f46 (diff) |
sunxi: dram: Drop DDR2 support and assume only single rank DDR3 memory
All the known Allwinner A10/A13/A20 devices are using just single rank
DDR3 memory. So don't pretend that we support DDR2 or more than one
rank, because nobody could ever test these configurations for real and
they are likely broken. Support for these features can be added back
in the case if such hardware actually exists.
As part of this code cleanup, also replace division by 1024 with
division by 1000 for the refresh timing calculations. This allows
to use the original non-skewed tRFC timing table from the DRR3 spec
and make code less confusing.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch/arm/cpu/armv7/sunxi/board.c')
0 files changed, 0 insertions, 0 deletions