diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2014-02-18 07:31:57 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-03-04 09:42:07 -0500 |
| commit | e27f2dd721d8121177cb32a63684557fa625d4bf (patch) | |
| tree | ae8a6a5e1b064ced5d268b61a193dbd3617b589f /arch/arm/cpu/armv7/tegra30 | |
| parent | 8feb37b9beefd4ba38227a837b6d7b3f5821b90c (diff) | |
ARM: AM4372: Update EMIF registers for DDR3
Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD
registers.
In EMIF_PHY_CTRL:
Updating [4:0]READ_LATENCY to 8, because at higher frequencies like
400MHz the read latency expected will be CL+3 as per tests from HW
folks.
Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug
purpose. With out this resume is not working(Still waiting for PHY team
to come back for better explanation).
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7/tegra30')
0 files changed, 0 insertions, 0 deletions