ARM: UniPhier: add DDR PHY training code

This training code provides run-time adjustment of DDR PHY parameters
for stable DDR operation.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

3 files changed, 96 insertions, 1 deletions

diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
index fd1c432f4f..cee78781f6 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
@@ -7,4 +7,4 @@ obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
 obj-y += boot-mode.o
 obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o
 obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
-obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
+obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o ddrphy_init.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c
new file mode 100644
index 0000000000..c5d1f606cf
--- /dev/null
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/arch/ddrphy-regs.h>
+
+void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+{
+	u32 tmp;
+
+	writel(0x0300c473, &phy->pgcr[1]);
+	if (freq == 1333) {
+		writel(0x0a806844, &phy->ptr[0]);
+		writel(0x208e0124, &phy->ptr[1]);
+	} else {
+		writel(0x0c807d04, &phy->ptr[0]);
+		writel(0x2710015E, &phy->ptr[1]);
+	}
+	writel(0x00083DEF, &phy->ptr[2]);
+	if (freq == 1333) {
+		writel(0x0f051616, &phy->ptr[3]);
+		writel(0x06ae08d6, &phy->ptr[4]);
+	} else {
+		writel(0x12061A80, &phy->ptr[3]);
+		writel(0x08027100, &phy->ptr[4]);
+	}
+	writel(0xF004001A, &phy->dsgcr);
+
+	/* change the value of the on-die pull-up/pull-down registors */
+	tmp = readl(&phy->dxccr);
+	tmp &= ~0x0ee0;
+	tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
+	writel(tmp, &phy->dxccr);
+
+	writel(0x0000040B, &phy->dcr);
+	if (freq == 1333) {
+		writel(0x85589955, &phy->dtpr[0]);
+		if (size == 1)
+			writel(0x1a8363c0, &phy->dtpr[1]);
+		else
+			writel(0x1a8363c0, &phy->dtpr[1]);
+		writel(0x5002c200, &phy->dtpr[2]);
+		writel(0x00000b51, &phy->mr0);
+	} else {
+		writel(0x999cbb66, &phy->dtpr[0]);
+		if (size == 1)
+			writel(0x1a878400, &phy->dtpr[1]);
+		else
+			writel(0x1a878400, &phy->dtpr[1]);
+		writel(0xa00214f8, &phy->dtpr[2]);
+		writel(0x00000d71, &phy->mr0);
+	}
+	writel(0x00000006, &phy->mr1);
+	if (freq == 1333)
+		writel(0x00000290, &phy->mr2);
+	else
+		writel(0x00000298, &phy->mr2);
+
+	writel(0x00000000, &phy->mr3);
+
+	while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+		;
+
+	writel(0x0300C473, &phy->pgcr[1]);
+	writel(0x0000005D, &phy->zq[0].cr[1]);
+}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c
index 328b2f4d9a..1973ab04c2 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/umc-regs.h>
+#include <asm/arch/ddrphy-regs.h>
 
 static inline void umc_start_ssif(void __iomem *ssif_base)
 {
@@ -94,6 +95,10 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
 	void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
 	void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
 	void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
+	void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
+	void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
+	void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
+	void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
 
 	umc_dram_init_start(dramcont0);
 	umc_dram_init_start(dramcont1);
@@ -102,12 +107,32 @@ static inline int umc_init_sub(int freq, int size_ch0, int size_ch1)
 
 	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
 
+	ddrphy_init(phy0_0, freq, size_ch0);
+
+	ddrphy_prepare_training(phy0_0, 0);
+	ddrphy_training(phy0_0);
+
 	writel(0x00000103, dramcont0 + UMC_DIOCTLA);
 
+	ddrphy_init(phy0_1, freq, size_ch0);
+
+	ddrphy_prepare_training(phy0_1, 1);
+	ddrphy_training(phy0_1);
+
 	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
 
+	ddrphy_init(phy1_0, freq, size_ch1);
+
+	ddrphy_prepare_training(phy1_0, 0);
+	ddrphy_training(phy1_0);
+
 	writel(0x00000103, dramcont1 + UMC_DIOCTLA);
 
+	ddrphy_init(phy1_1, freq, size_ch1);
+
+	ddrphy_prepare_training(phy1_1, 1);
+	ddrphy_training(phy1_1);
+
 	umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
 	umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);