diff options
| author | Khoronzhuk, Ivan <ivan.khoronzhuk@ti.com> | 2014-10-17 21:01:16 +0300 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-10-23 11:27:29 -0400 |
| commit | 69a3b811411d7f7d58c1ad587412451e7d4ed412 (patch) | |
| tree | af057747679dbe4a6d48aa97865b8626133f20d2 /arch/arm/cpu/armv7 | |
| parent | c05d05e7202b01a1b461c78ba6c5b06545621620 (diff) | |
ARM: keystone: clock: add support for K2E SoCs
For K2E and K2L SoCs clock output from PASS PLL has to be enabled
after NETCP domain and PA module are enabled. So create new function
for that and call it after PA module is enabled.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/keystone/clock.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c index 47fc89398d..d13fbc1a4b 100644 --- a/arch/arm/cpu/armv7/keystone/clock.c +++ b/arch/arm/cpu/armv7/keystone/clock.c @@ -185,10 +185,6 @@ void init_pll(const struct pll_init_data *data) tmp &= ~(PLL_BWADJ_HI_MASK); tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK); - /* set PLL Select (bit 13) for PASS PLL */ - if (data->pll == PASS_PLL) - tmp |= PLLCTL_PAPLL; - __raw_writel(tmp, keystone_pll_regs[data->pll].reg1); /* Reset bit: bit 14 for both DDR3 & PASS PLL */ @@ -261,3 +257,16 @@ inline int get_max_arm_speed(void) return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds); } #endif + +void pass_pll_pa_clk_enable(void) +{ + u32 reg; + + reg = readl(keystone_pll_regs[PASS_PLL].reg1); + + reg |= PLLCTL_PAPLL; + writel(reg, keystone_pll_regs[PASS_PLL].reg1); + + /* wait till clock is enabled */ + sdelay(15000); +} |