diff options
| author | Hans de Goede <hdegoede@redhat.com> | 2015-04-12 11:46:41 +0200 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-05-04 16:51:51 +0200 |
| commit | 886a7b45ef48e97a8d4a226a3a3d84b5f89b4ee2 (patch) | |
| tree | 07766a7c5c88a45b7ab646f09a0596912bdfda30 /arch/arm/cpu/armv7 | |
| parent | 5e6bacdb84dbf5cb3b24498784807c3f3c7bdeb4 (diff) | |
sunxi: Add support for A33 PLL11 (second DRAM pll)
Add support for the new second DRAM PLL found on the A33 SoC.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index e2a78676b1..3bfa122ec0 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -170,6 +170,24 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable) udelay(5500); } +#ifdef CONFIG_MACH_SUN8I_A33 +void clock_set_pll11(unsigned int clk, bool sigma_delta_enable) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (sigma_delta_enable) + writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg); + + writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD | + (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) | + CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg); + + while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD) + ; +} +#endif + unsigned int clock_get_pll6(void) { struct sunxi_ccm_reg *const ccm = |