Merge branch 'master' of git://git.denx.de/u-boot-arm

3 files changed, 34 insertions, 1 deletions

diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
index 5024fc55e2..0859e443d8 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -13,7 +13,7 @@ include $(TOPDIR)/config.mk
 LIB	=  $(obj)lib$(SOC).o
 
 SOBJS	:= lowlevel_init.o
-COBJS-y	:= misc.o timer.o reset_manager.o
+COBJS-y	:= misc.o timer.o reset_manager.o system_manager.o
 COBJS-$(CONFIG_SPL_BUILD) += spl.o
 
 COBJS	:= $(COBJS-y)
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 2b9be28c21..74bceab183 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -12,6 +12,7 @@
 #include <image.h>
 #include <asm/arch/reset_manager.h>
 #include <spl.h>
+#include <asm/arch/system_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -25,6 +26,11 @@ u32 spl_boot_device(void)
  */
 void spl_board_init(void)
 {
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+	/* configure the pin muxing through system manager */
+	sysmgr_pinmux_init();
+#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
+
 	/* de-assert reset for peripherals and bridges based on handoff */
 	reset_deassert_peripherals_handoff();
 
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c
new file mode 100644
index 0000000000..d96521ba03
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -0,0 +1,27 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/system_manager.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Configure all the pin muxes
+ */
+void sysmgr_pinmux_init(void)
+{
+	unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
+
+	const unsigned long *pval = sys_mgr_init_table;
+	unsigned long i;
+
+	for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table);
+		i++, offset += sizeof(unsigned long)) {
+		writel(*pval++, (SOCFPGA_SYSMGR_ADDRESS + offset));
+	}
+}