Merge branch 'master' of git://git.denx.de/u-boot

59 files changed, 808 insertions, 4184 deletions

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 409e6f5651..b228ed6a2e 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,6 @@ obj-$(CONFIG_IPROC) += iproc-common/
 obj-$(CONFIG_KONA) += kona-common/
 obj-$(CONFIG_OMAP_COMMON) += omap-common/
 obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o
-obj-$(CONFIG_TEGRA) += tegra-common/
 
 ifneq (,$(filter s5pc1xx exynos,$(SOC)))
 obj-y += s5p-common/
@@ -40,13 +39,11 @@ endif
 
 obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
 obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
-obj-$(CONFIG_AT91FAMILY) += at91/
+obj-$(CONFIG_BCM2835) += bcm2835/
 obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
 obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
 obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
 obj-$(CONFIG_ARCH_EXYNOS) += exynos/
-obj-$(CONFIG_ARCH_HIGHBANK) += highbank/
-obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
 obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
 obj-$(if $(filter mx5,$(SOC)),y) += mx5/
 obj-$(CONFIG_MX6) += mx6/
@@ -58,7 +55,6 @@ obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
 obj-$(CONFIG_SOCFPGA) += socfpga/
 obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
 obj-$(CONFIG_ARCH_SUNXI) += sunxi/
-obj-$(CONFIG_TEGRA20) += tegra20/
 obj-$(CONFIG_U8500) += u8500/
 obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
 obj-$(CONFIG_VF610) += vf610/
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 31188c85bc..529a119514 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -118,4 +118,7 @@ void enable_basic_clocks(void)
 
 	/* Select the Master osc clk as Timer2 clock source */
 	writel(0x1, &cmdpll->clktimer2clk);
+
+	/* For OPP100 the mac clock should be /5. */
+	writel(0x4, &cmdpll->clkselmacclk);
 }
diff --git a/arch/arm/cpu/armv7/at91/Makefile b/arch/arm/cpu/armv7/at91/Makefile
deleted file mode 100644
index f4f35a4bc1..0000000000
--- a/arch/arm/cpu/armv7/at91/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2013
-# Bo Shen <voice.shen@atmel.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-$(CONFIG_SAMA5D3)	+= sama5d3_devices.o
-obj-$(CONFIG_SAMA5D4)	+= sama5d4_devices.o
-obj-y += clock.o
-obj-y += cpu.o
-obj-y += reset.o
-obj-y += timer.o
diff --git a/arch/arm/cpu/armv7/at91/clock.c b/arch/arm/cpu/armv7/at91/clock.c
deleted file mode 100644
index 0bf453eff5..0000000000
--- a/arch/arm/cpu/armv7/at91/clock.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
- *
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-
-#if !defined(CONFIG_AT91FAMILY)
-# error You need to define CONFIG_AT91FAMILY in your board config!
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static unsigned long at91_css_to_rate(unsigned long css)
-{
-	switch (css) {
-	case AT91_PMC_MCKR_CSS_SLOW:
-		return CONFIG_SYS_AT91_SLOW_CLOCK;
-	case AT91_PMC_MCKR_CSS_MAIN:
-		return gd->arch.main_clk_rate_hz;
-	case AT91_PMC_MCKR_CSS_PLLA:
-		return gd->arch.plla_rate_hz;
-	}
-
-	return 0;
-}
-
-static u32 at91_pll_rate(u32 freq, u32 reg)
-{
-	unsigned mul, div;
-
-	div = reg & 0xff;
-	mul = (reg >> 18) & 0x7f;
-	if (div && mul) {
-		freq /= div;
-		freq *= mul + 1;
-	} else {
-		freq = 0;
-	}
-
-	return freq;
-}
-
-int at91_clock_init(unsigned long main_clock)
-{
-	unsigned freq, mckr;
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-	unsigned tmp;
-	/*
-	 * When the bootloader initialized the main oscillator correctly,
-	 * there's no problem using the cycle counter.  But if it didn't,
-	 * or when using oscillator bypass mode, we must be told the speed
-	 * of the main clock.
-	 */
-	if (!main_clock) {
-		do {
-			tmp = readl(&pmc->mcfr);
-		} while (!(tmp & AT91_PMC_MCFR_MAINRDY));
-		tmp &= AT91_PMC_MCFR_MAINF_MASK;
-		main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
-	}
-#endif
-	gd->arch.main_clk_rate_hz = main_clock;
-
-	/* report if PLLA is more than mildly overclocked */
-	gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
-
-	/*
-	 * MCK and CPU derive from one of those primary clocks.
-	 * For now, assume this parentage won't change.
-	 */
-	mckr = readl(&pmc->mckr);
-
-	/* plla divisor by 2 */
-	if (mckr & (1 << 12))
-		gd->arch.plla_rate_hz >>= 1;
-
-	gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
-	freq = gd->arch.mck_rate_hz;
-
-	/* prescale */
-	freq >>= mckr & AT91_PMC_MCKR_PRES_MASK;
-
-	switch (mckr & AT91_PMC_MCKR_MDIV_MASK) {
-	case AT91_PMC_MCKR_MDIV_2:
-		gd->arch.mck_rate_hz = freq / 2;
-		break;
-	case AT91_PMC_MCKR_MDIV_3:
-		gd->arch.mck_rate_hz = freq / 3;
-		break;
-	case AT91_PMC_MCKR_MDIV_4:
-		gd->arch.mck_rate_hz = freq / 4;
-		break;
-	default:
-		break;
-	}
-
-	gd->arch.cpu_clk_rate_hz = freq;
-
-	return 0;
-}
-
-void at91_plla_init(u32 pllar)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	writel(pllar, &pmc->pllar);
-	while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
-		;
-}
-
-void at91_mck_init(u32 mckr)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	u32 tmp;
-
-	tmp = readl(&pmc->mckr);
-	tmp &= ~(AT91_PMC_MCKR_CSS_MASK  |
-		 AT91_PMC_MCKR_PRES_MASK |
-		 AT91_PMC_MCKR_MDIV_MASK |
-		 AT91_PMC_MCKR_PLLADIV_2);
-#ifdef CPU_HAS_H32MXDIV
-	tmp &= ~AT91_PMC_MCKR_H32MXDIV;
-#endif
-
-	tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK  |
-		       AT91_PMC_MCKR_PRES_MASK |
-		       AT91_PMC_MCKR_MDIV_MASK |
-		       AT91_PMC_MCKR_PLLADIV_2);
-#ifdef CPU_HAS_H32MXDIV
-	tmp |= mckr & AT91_PMC_MCKR_H32MXDIV;
-#endif
-
-	writel(tmp, &pmc->mckr);
-
-	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
-		;
-}
-
-void at91_periph_clk_enable(int id)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	u32 regval;
-
-	if (id > AT91_PMC_PCR_PID_MASK)
-		return;
-
-	regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id;
-
-	writel(regval, &pmc->pcr);
-}
-
-void at91_periph_clk_disable(int id)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-	u32 regval;
-
-	if (id > AT91_PMC_PCR_PID_MASK)
-		return;
-
-	regval = AT91_PMC_PCR_CMD_WRITE | id;
-
-	writel(regval, &pmc->pcr);
-}
diff --git a/arch/arm/cpu/armv7/at91/config.mk b/arch/arm/cpu/armv7/at91/config.mk
deleted file mode 100644
index db6030880f..0000000000
--- a/arch/arm/cpu/armv7/at91/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) 2014, Andreas Bießmann <andreas.devel@googlemail.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-ifndef CONFIG_SPL_BUILD
-ALL-y	+= u-boot.img
-endif
diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/cpu/armv7/at91/cpu.c
deleted file mode 100644
index 8d86f97e3d..0000000000
--- a/arch/arm/cpu/armv7/at91/cpu.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- * (C) Copyright 2009
- * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- * (C) Copyright 2013
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_dbu.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_gpbr.h>
-#include <asm/arch/clk.h>
-
-#ifndef CONFIG_SYS_AT91_MAIN_CLOCK
-#define CONFIG_SYS_AT91_MAIN_CLOCK 0
-#endif
-
-int arch_cpu_init(void)
-{
-	return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
-}
-
-void arch_preboot_os(void)
-{
-	ulong cpiv;
-	at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
-
-	cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir));
-
-	/*
-	 * Disable PITC
-	 * Add 0x1000 to current counter to stop it faster
-	 * without waiting for wrapping back to 0
-	 */
-	writel(cpiv + 0x1000, &pit->mr);
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo(void)
-{
-	char buf[32];
-
-	printf("CPU: %s\n", get_cpu_name());
-	printf("Crystal frequency: %8s MHz\n",
-	       strmhz(buf, get_main_clk_rate()));
-	printf("CPU clock        : %8s MHz\n",
-	       strmhz(buf, get_cpu_clk_rate()));
-	printf("Master clock     : %8s MHz\n",
-	       strmhz(buf, get_mck_clk_rate()));
-
-	return 0;
-}
-#endif
-
-void enable_caches(void)
-{
-	icache_enable();
-	dcache_enable();
-}
-
-unsigned int get_chip_id(void)
-{
-	return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK;
-}
-
-unsigned int get_extension_chip_id(void)
-{
-	return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID);
-}
diff --git a/arch/arm/cpu/armv7/at91/reset.c b/arch/arm/cpu/armv7/at91/reset.c
deleted file mode 100644
index b30e79b60a..0000000000
--- a/arch/arm/cpu/armv7/at91/reset.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2013
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_rstc.h>
-
-/* Reset the cpu by telling the reset controller to do so */
-void reset_cpu(ulong ignored)
-{
-	at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
-
-	writel(AT91_RSTC_KEY
-		| AT91_RSTC_CR_PROCRST	/* Processor Reset */
-		| AT91_RSTC_CR_PERRST	/* Peripheral Reset */
-#ifdef CONFIG_AT91RESET_EXTRST
-		| AT91_RSTC_CR_EXTRST	/* External Reset (assert nRST pin) */
-#endif
-		, &rstc->cr);
-	/* never reached */
-	do { } while (1);
-}
diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c
deleted file mode 100644
index 78ecfc882a..0000000000
--- a/arch/arm/cpu/armv7/at91/sama5d3_devices.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * Copyright (C) 2012-2013 Atmel Corporation
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/sama5d3.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/io.h>
-
-unsigned int has_emac()
-{
-	return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36();
-}
-
-unsigned int has_gmac()
-{
-	return !cpu_is_sama5d31();
-}
-
-unsigned int has_lcdc()
-{
-	return !cpu_is_sama5d35();
-}
-
-char *get_cpu_name()
-{
-	unsigned int extension_id = get_extension_chip_id();
-
-	if (cpu_is_sama5d3())
-		switch (extension_id) {
-		case ARCH_EXID_SAMA5D31:
-			return "SAMA5D31";
-		case ARCH_EXID_SAMA5D33:
-			return "SAMA5D33";
-		case ARCH_EXID_SAMA5D34:
-			return "SAMA5D34";
-		case ARCH_EXID_SAMA5D35:
-			return "SAMA5D35";
-		case ARCH_EXID_SAMA5D36:
-			return "SAMA5D36";
-		default:
-			return "Unknown CPU type";
-		}
-	else
-		return "Unknown CPU type";
-}
-
-void at91_serial0_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTD, 18, 1);	/* TXD0 */
-	at91_set_a_periph(AT91_PIO_PORTD, 17, 0);	/* RXD0 */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_USART0);
-}
-
-void at91_serial1_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTB, 29, 1);	/* TXD1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 28, 0);	/* RXD1 */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_USART1);
-}
-
-void at91_serial2_hw_init(void)
-{
-	at91_set_b_periph(AT91_PIO_PORTE, 26, 1);	/* TXD2 */
-	at91_set_b_periph(AT91_PIO_PORTE, 25, 0);	/* RXD2 */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_USART2);
-}
-
-void at91_seriald_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTB, 31, 1);	/* DTXD */
-	at91_set_a_periph(AT91_PIO_PORTB, 30, 0);	/* DRXD */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_DBGU);
-}
-
-#if defined(CONFIG_ATMEL_SPI)
-void at91_spi0_hw_init(unsigned long cs_mask)
-{
-	at91_set_a_periph(AT91_PIO_PORTD, 10, 0);       /* SPI0_MISO */
-	at91_set_a_periph(AT91_PIO_PORTD, 11, 0);       /* SPI0_MOSI */
-	at91_set_a_periph(AT91_PIO_PORTD, 12, 0);       /* SPI0_SPCK */
-
-	if (cs_mask & (1 << 0))
-		at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
-	if (cs_mask & (1 << 1))
-		at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
-	if (cs_mask & (1 << 2))
-		at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
-	if (cs_mask & (1 << 3))
-		at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_SPI0);
-}
-#endif
-
-#ifdef CONFIG_GENERIC_ATMEL_MCI
-void at91_mci_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTD, 0, 0);	/* MCI0 CMD */
-	at91_set_a_periph(AT91_PIO_PORTD, 1, 0);	/* MCI0 DA0 */
-	at91_set_a_periph(AT91_PIO_PORTD, 2, 0);	/* MCI0 DA1 */
-	at91_set_a_periph(AT91_PIO_PORTD, 3, 0);        /* MCI0 DA2 */
-	at91_set_a_periph(AT91_PIO_PORTD, 4, 0);        /* MCI0 DA3 */
-#ifdef CONFIG_ATMEL_MCI_8BIT
-	at91_set_a_periph(AT91_PIO_PORTD, 5, 0);        /* MCI0 DA4 */
-	at91_set_a_periph(AT91_PIO_PORTD, 6, 0);        /* MCI0 DA5 */
-	at91_set_a_periph(AT91_PIO_PORTD, 7, 0);        /* MCI0 DA6 */
-	at91_set_a_periph(AT91_PIO_PORTD, 8, 0);        /* MCI0 DA7 */
-#endif
-	at91_set_a_periph(AT91_PIO_PORTD, 9, 0);        /* MCI0 CLK */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_MCI0);
-}
-#endif
-
-#ifdef CONFIG_MACB
-void at91_macb_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* ETXCK_EREFCK */
-	at91_set_a_periph(AT91_PIO_PORTC, 5, 0);	/* ERXDV */
-	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* ERX0 */
-	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* ERX1 */
-	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* ERXER */
-	at91_set_a_periph(AT91_PIO_PORTC, 4, 0);	/* ETXEN */
-	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* ETX0 */
-	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* ETX1 */
-	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* EMDIO */
-	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* EMDC */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_EMAC);
-}
-
-void at91_gmac_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* GTX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* GTX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* GTX2 */
-	at91_set_a_periph(AT91_PIO_PORTB, 3, 0);	/* GTX3 */
-	at91_set_a_periph(AT91_PIO_PORTB, 4, 0);	/* GRX0 */
-	at91_set_a_periph(AT91_PIO_PORTB, 5, 0);	/* GRX1 */
-	at91_set_a_periph(AT91_PIO_PORTB, 6, 0);	/* GRX2 */
-	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* GRX3 */
-	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* GTXCK */
-	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* GTXEN */
-
-	at91_set_a_periph(AT91_PIO_PORTB, 11, 0);	/* GRXCK */
-	at91_set_a_periph(AT91_PIO_PORTB, 13, 0);	/* GRXER */
-
-	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* GMDC */
-	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* GMDIO */
-	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* G125CK */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_GMAC);
-}
-#endif
-
-#ifdef CONFIG_LCD
-void at91_lcd_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTA, 24, 0);	/* LCDPWM */
-	at91_set_a_periph(AT91_PIO_PORTA, 25, 0);	/* LCDDISP */
-	at91_set_a_periph(AT91_PIO_PORTA, 26, 0);	/* LCDVSYNC */
-	at91_set_a_periph(AT91_PIO_PORTA, 27, 0);	/* LCDHSYNC */
-	at91_set_a_periph(AT91_PIO_PORTA, 28, 0);	/* LCDDOTCK */
-	at91_set_a_periph(AT91_PIO_PORTA, 29, 0);	/* LCDDEN */
-
-	/* The lower 16-bit of LCD only available on Port A */
-	at91_set_a_periph(AT91_PIO_PORTA,  0, 0);	/* LCDD0 */
-	at91_set_a_periph(AT91_PIO_PORTA,  1, 0);	/* LCDD1 */
-	at91_set_a_periph(AT91_PIO_PORTA,  2, 0);	/* LCDD2 */
-	at91_set_a_periph(AT91_PIO_PORTA,  3, 0);	/* LCDD3 */
-	at91_set_a_periph(AT91_PIO_PORTA,  4, 0);	/* LCDD4 */
-	at91_set_a_periph(AT91_PIO_PORTA,  5, 0);	/* LCDD5 */
-	at91_set_a_periph(AT91_PIO_PORTA,  6, 0);	/* LCDD6 */
-	at91_set_a_periph(AT91_PIO_PORTA,  7, 0);	/* LCDD7 */
-	at91_set_a_periph(AT91_PIO_PORTA,  8, 0);	/* LCDD8 */
-	at91_set_a_periph(AT91_PIO_PORTA,  9, 0);	/* LCDD9 */
-	at91_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* LCDD10 */
-	at91_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* LCDD11 */
-	at91_set_a_periph(AT91_PIO_PORTA, 12, 0);	/* LCDD12 */
-	at91_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* LCDD13 */
-	at91_set_a_periph(AT91_PIO_PORTA, 14, 0);	/* LCDD14 */
-	at91_set_a_periph(AT91_PIO_PORTA, 15, 0);	/* LCDD15 */
-
-	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_LCDC);
-}
-#endif
-
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-void at91_udp_hw_init(void)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	/* Enable UPLL clock */
-	writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
-	/* Enable UDPHS clock */
-	at91_periph_clk_enable(ATMEL_ID_UDPHS);
-}
-#endif
diff --git a/arch/arm/cpu/armv7/at91/sama5d4_devices.c b/arch/arm/cpu/armv7/at91/sama5d4_devices.c
deleted file mode 100644
index ef39cb7e08..0000000000
--- a/arch/arm/cpu/armv7/at91/sama5d4_devices.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (C) 2014 Atmel
- *		      Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/sama5_matrix.h>
-#include <asm/arch/sama5_sfr.h>
-#include <asm/arch/sama5d4.h>
-
-char *get_cpu_name()
-{
-	unsigned int extension_id = get_extension_chip_id();
-
-	if (cpu_is_sama5d4())
-		switch (extension_id) {
-		case ARCH_EXID_SAMA5D41:
-			return "SAMA5D41";
-		case ARCH_EXID_SAMA5D42:
-			return "SAMA5D42";
-		case ARCH_EXID_SAMA5D43:
-			return "SAMA5D43";
-		case ARCH_EXID_SAMA5D44:
-			return "SAMA5D44";
-		default:
-			return "Unknown CPU type";
-		}
-	else
-		return "Unknown CPU type";
-}
-
-#ifdef CONFIG_USB_GADGET_ATMEL_USBA
-void at91_udp_hw_init(void)
-{
-	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
-	/* Enable UPLL clock */
-	writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr);
-	/* Enable UDPHS clock */
-	at91_periph_clk_enable(ATMEL_ID_UDPHS);
-}
-#endif
-
-#ifdef CONFIG_SPL_BUILD
-void matrix_init(void)
-{
-	struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0;
-	struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
-	int i;
-
-	/* Disable the write protect */
-	writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
-	writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
-
-	/* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
-	for (i = 4; i <= 10; i++) {
-		writel(0x000f0f0f, &h64mx->ssr[i]);
-		writel(0x0000ffff, &h64mx->sassr[i]);
-		writel(0x0000000f, &h64mx->srtsr[i]);
-	}
-
-	/* CS3 */
-	writel(0x00c0c0c0, &h32mx->ssr[3]);
-	writel(0xff000000, &h32mx->sassr[3]);
-	writel(0xff000000, &h32mx->srtsr[3]);
-
-	/* NFC SRAM */
-	writel(0x00010101, &h32mx->ssr[4]);
-	writel(0x00000001, &h32mx->sassr[4]);
-	writel(0x00000001, &h32mx->srtsr[4]);
-
-	/* Enable the write protect */
-	writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
-	writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
-}
-
-void redirect_int_from_saic_to_aic(void)
-{
-	struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
-	u32 key32;
-
-	if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
-		key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
-		writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
-	}
-}
-#endif
diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c
deleted file mode 100644
index 19bf80ba7e..0000000000
--- a/arch/arm/cpu/armv7/at91/timer.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * (C) Copyright 2007-2008
- * Stelian Pop <stelian@popies.net>
- * Lead Tech Design <www.leadtechdesign.com>
- *
- * (C) Copyright 2013
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/at91_pit.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/clk.h>
-#include <div64.h>
-
-#if !defined(CONFIG_AT91FAMILY)
-# error You need to define CONFIG_AT91FAMILY in your board config!
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * We're using the SAMA5D3x PITC in 32 bit mode, by
- * setting the 20 bit counter period to its maximum (0xfffff).
- * (See the relevant data sheets to understand that this really works)
- *
- * We do also mimic the typical powerpc way of incrementing
- * two 32 bit registers called tbl and tbu.
- *
- * Those registers increment at 1/16 the main clock rate.
- */
-
-#define TIMER_LOAD_VAL	0xfffff
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, gd->arch.timer_rate_hz);
-
-	return tick;
-}
-
-static inline unsigned long long usec_to_tick(unsigned long long usec)
-{
-	usec *= gd->arch.timer_rate_hz;
-	do_div(usec, 1000000);
-
-	return usec;
-}
-
-/*
- * Use the PITC in full 32 bit incrementing mode
- */
-int timer_init(void)
-{
-	at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
-
-	/* Enable PITC Clock */
-	at91_periph_clk_enable(ATMEL_ID_PIT);
-
-	/* Enable PITC */
-	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
-
-	gd->arch.timer_rate_hz = get_pit_clk_rate() / 16;
-
-	gd->arch.tbu = 0;
-	gd->arch.tbl = 0;
-
-	return 0;
-}
-
-/*
- * Get the current 64 bit timer tick count
- */
-unsigned long long get_ticks(void)
-{
-	at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
-
-	ulong now = readl(&pit->piir);
-
-	/* increment tbu if tbl has rolled over */
-	if (now < gd->arch.tbl)
-		gd->arch.tbu++;
-	gd->arch.tbl = now;
-	return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned long long start;
-	ulong tmo;
-
-	start = get_ticks();		/* get current timestamp */
-	tmo = usec_to_tick(usec);	/* convert usecs to ticks */
-	while ((get_ticks() - start) < tmo)
-		;			/* loop till time has passed */
-}
-
-/*
- * get_timer(base) can be used to check for timeouts or
- * to measure elasped time relative to an event:
- *
- * ulong start_time = get_timer(0) sets start_time to the current
- * time value.
- * get_timer(start_time) returns the time elapsed since then.
- *
- * The time is used in CONFIG_SYS_HZ units!
- */
-ulong get_timer(ulong base)
-{
-	return tick_to_time(get_ticks()) - base;
-}
-
-/*
- * Return the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return gd->arch.timer_rate_hz;
-}
diff --git a/arch/arm/cpu/armv7/bcm2835/Makefile b/arch/arm/cpu/armv7/bcm2835/Makefile
new file mode 100644
index 0000000000..ed1ee4753d
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm2835/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2012 Stephen Warren
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+src_dir := ../../arm1176/bcm2835/
+
+obj-y	:=
+obj-y	+= $(src_dir)/init.o
+obj-y	+= $(src_dir)/reset.o
+obj-y	+= $(src_dir)/timer.o
+obj-y	+= $(src_dir)/mbox.o
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
index 7fcb5d2094..eb86a7fe7d 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -6,7 +6,7 @@ choice
 config TARGET_SMDKV310
 	select SUPPORT_SPL
 	bool "Exynos4210 SMDKV310 board"
-	select OF_CONTROL if !SPL_BUILD
+	select OF_CONTROL
 
 config TARGET_TRATS
 	bool "Exynos4210 Trats board"
@@ -33,38 +33,59 @@ config TARGET_ARNDALE
 	select CPU_V7_HAS_NONSEC
 	select CPU_V7_HAS_VIRT
 	select SUPPORT_SPL
-	select OF_CONTROL if !SPL_BUILD
+	select OF_CONTROL
 
 config TARGET_SMDK5250
 	bool "SMDK5250 board"
 	select SUPPORT_SPL
-	select OF_CONTROL if !SPL_BUILD
+	select OF_CONTROL
 
 config TARGET_SNOW
 	bool "Snow board"
 	select SUPPORT_SPL
-	select OF_CONTROL if !SPL_BUILD
+	select OF_CONTROL
 
 config TARGET_SMDK5420
 	bool "SMDK5420 board"
 	select SUPPORT_SPL
-	select OF_CONTROL if !SPL_BUILD
+	select OF_CONTROL
 
 config TARGET_PEACH_PI
 	bool "Peach Pi board"
 	select SUPPORT_SPL
-	select OF_CONTROL if !SPL_BUILD
+	select OF_CONTROL
 
 config TARGET_PEACH_PIT
 	bool "Peach Pit board"
 	select SUPPORT_SPL
-	select OF_CONTROL if !SPL_BUILD
+	select OF_CONTROL
 
 endchoice
 
 config SYS_SOC
 	default "exynos"
 
+config DM
+	default y
+
+config DM_SERIAL
+	default y
+
+config DM_SPI
+	default y
+
+config DM_SPI_FLASH
+	default y
+
+config DM_GPIO
+	default y
+
+config SYS_MALLOC_F
+	default y
+
+config SYS_MALLOC_F_LEN
+	default 0x400
+
 source "board/samsung/smdkv310/Kconfig"
 source "board/samsung/trats/Kconfig"
 source "board/samsung/universal_c210/Kconfig"
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index b31c13b14b..c6455c2f3c 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -20,42 +20,84 @@
  * positions of the peripheral clocks of the src and div registers
  */
 struct clk_bit_info {
+	enum periph_id id;
+	int32_t src_mask;
+	int32_t div_mask;
+	int32_t prediv_mask;
 	int8_t src_bit;
 	int8_t div_bit;
 	int8_t prediv_bit;
 };
 
-/* src_bit div_bit prediv_bit */
-static struct clk_bit_info clk_bit_info[] = {
-	{0,	0,	-1},
-	{4,	4,	-1},
-	{8,	8,	-1},
-	{12,	12,	-1},
-	{0,	0,	8},
-	{4,	16,	24},
-	{8,	0,	8},
-	{12,	16,	24},
-	{-1,	-1,	-1},
-	{16,	0,	8},
-	{20,	16,	24},
-	{24,	0,	8},
-	{0,	0,	4},
-	{4,	12,	16},
-	{-1,	-1,	-1},
-	{-1,	-1,	-1},
-	{-1,	24,	0},
-	{-1,	24,	0},
-	{-1,	24,	0},
-	{-1,	24,	0},
-	{-1,	24,	0},
-	{-1,	24,	0},
-	{-1,	24,	0},
-	{-1,	24,	0},
-	{24,	0,	-1},
-	{24,	0,	-1},
-	{24,	0,	-1},
-	{24,	0,	-1},
-	{24,	0,	-1},
+static struct clk_bit_info exynos5_bit_info[] = {
+	/* periph id		s_mask	d_mask	p_mask	s_bit	d_bit	p_bit */
+	{PERIPH_ID_UART0,	0xf,	0xf,	-1,	0,	0,	-1},
+	{PERIPH_ID_UART1,	0xf,	0xf,	-1,	4,	4,	-1},
+	{PERIPH_ID_UART2,	0xf,	0xf,	-1,	8,	8,	-1},
+	{PERIPH_ID_UART3,	0xf,	0xf,	-1,	12,	12,	-1},
+	{PERIPH_ID_I2C0,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_I2C1,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_I2C2,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_I2C3,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_I2C4,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_I2C5,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_I2C6,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_I2C7,	-1,	0x7,	0x7,	-1,	24,	0},
+	{PERIPH_ID_SPI0,	0xf,	0xf,	0xff,	16,	0,	8},
+	{PERIPH_ID_SPI1,	0xf,	0xf,	0xff,	20,	16,	24},
+	{PERIPH_ID_SPI2,	0xf,	0xf,	0xff,	24,	0,	8},
+	{PERIPH_ID_SDMMC0,	0xf,	0xf,	0xff,	0,	0,	8},
+	{PERIPH_ID_SDMMC1,	0xf,	0xf,	0xff,	4,	16,	24},
+	{PERIPH_ID_SDMMC2,	0xf,	0xf,	0xff,	8,	0,	8},
+	{PERIPH_ID_SDMMC3,	0xf,	0xf,	0xff,	12,	16,	24},
+	{PERIPH_ID_I2S0,	0xf,	0xf,	0xff,	0,	0,	4},
+	{PERIPH_ID_I2S1,	0xf,	0xf,	0xff,	4,	12,	16},
+	{PERIPH_ID_SPI3,	0xf,	0xf,	0xff,	0,	0,	4},
+	{PERIPH_ID_SPI4,	0xf,	0xf,	0xff,	4,	12,	16},
+	{PERIPH_ID_SDMMC4,	0xf,	0xf,	0xff,	16,	0,	8},
+	{PERIPH_ID_PWM0,	0xf,	0xf,	-1,	24,	0,	-1},
+	{PERIPH_ID_PWM1,	0xf,	0xf,	-1,	24,	0,	-1},
+	{PERIPH_ID_PWM2,	0xf,	0xf,	-1,	24,	0,	-1},
+	{PERIPH_ID_PWM3,	0xf,	0xf,	-1,	24,	0,	-1},
+	{PERIPH_ID_PWM4,	0xf,	0xf,	-1,	24,	0,	-1},
+
+	{PERIPH_ID_NONE,	-1,	-1,	-1,	-1,	-1,	-1},
+};
+
+static struct clk_bit_info exynos542x_bit_info[] = {
+	/* periph id		s_mask	d_mask	p_mask	s_bit	d_bit	p_bit */
+	{PERIPH_ID_UART0,	0xf,	0xf,	-1,	4,	8,	-1},
+	{PERIPH_ID_UART1,	0xf,	0xf,	-1,	8,	12,	-1},
+	{PERIPH_ID_UART2,	0xf,	0xf,	-1,	12,	16,	-1},
+	{PERIPH_ID_UART3,	0xf,	0xf,	-1,	16,	20,	-1},
+	{PERIPH_ID_I2C0,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C1,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C2,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C3,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C4,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C5,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C6,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C7,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_SPI0,	0xf,	0xf,	0xff,	20,	20,	8},
+	{PERIPH_ID_SPI1,	0xf,	0xf,	0xff,	24,	24,	16},
+	{PERIPH_ID_SPI2,	0xf,	0xf,	0xff,	28,	28,	24},
+	{PERIPH_ID_SDMMC0,	0x7,	0x3ff,	-1,	8,	0,	-1},
+	{PERIPH_ID_SDMMC1,	0x7,	0x3ff,	-1,	12,	10,	-1},
+	{PERIPH_ID_SDMMC2,	0x7,	0x3ff,	-1,	16,	20,	-1},
+	{PERIPH_ID_I2C8,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2C9,	-1,	0x3f,	-1,	-1,	8,	-1},
+	{PERIPH_ID_I2S0,	0xf,	0xf,	0xff,	0,	0,	4},
+	{PERIPH_ID_I2S1,	0xf,	0xf,	0xff,	4,	12,	16},
+	{PERIPH_ID_SPI3,	0xf,	0xf,	0xff,	12,	16,	0},
+	{PERIPH_ID_SPI4,	0xf,	0xf,	0xff,	16,	20,	8},
+	{PERIPH_ID_PWM0,	0xf,	0xf,	-1,	24,	28,	-1},
+	{PERIPH_ID_PWM1,	0xf,	0xf,	-1,	24,	28,	-1},
+	{PERIPH_ID_PWM2,	0xf,	0xf,	-1,	24,	28,	-1},
+	{PERIPH_ID_PWM3,	0xf,	0xf,	-1,	24,	28,	-1},
+	{PERIPH_ID_PWM4,	0xf,	0xf,	-1,	24,	28,	-1},
+	{PERIPH_ID_I2C10,	-1,	0x3f,	-1,	-1,	8,	-1},
+
+	{PERIPH_ID_NONE,	-1,	-1,	-1,	-1,	-1,	-1},
 };
 
 /* Epll Clock division values to achive different frequency output */
@@ -260,11 +302,72 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
 	return fout;
 }
 
+/* exynos542x: return pll clock frequency */
+static unsigned long exynos542x_get_pll_clk(int pllreg)
+{
+	struct exynos5420_clock *clk =
+		(struct exynos5420_clock *)samsung_get_base_clock();
+	unsigned long r, k = 0;
+
+	switch (pllreg) {
+	case APLL:
+		r = readl(&clk->apll_con0);
+		break;
+	case MPLL:
+		r = readl(&clk->mpll_con0);
+		break;
+	case EPLL:
+		r = readl(&clk->epll_con0);
+		k = readl(&clk->epll_con1);
+		break;
+	case VPLL:
+		r = readl(&clk->vpll_con0);
+		k = readl(&clk->vpll_con1);
+		break;
+	case BPLL:
+		r = readl(&clk->bpll_con0);
+		break;
+	case RPLL:
+		r = readl(&clk->rpll_con0);
+		k = readl(&clk->rpll_con1);
+		break;
+	case SPLL:
+		r = readl(&clk->spll_con0);
+		break;
+	default:
+		printf("Unsupported PLL (%d)\n", pllreg);
+		return 0;
+	}
+
+	return exynos_get_pll_clk(pllreg, r, k);
+}
+
+static struct clk_bit_info *get_clk_bit_info(int peripheral)
+{
+	int i;
+	struct clk_bit_info *info;
+
+	if (proid_is_exynos5420() || proid_is_exynos5800())
+		info = exynos542x_bit_info;
+	else
+		info = exynos5_bit_info;
+
+	for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
+		if (info[i].id == peripheral)
+			break;
+	}
+
+	if (info[i].id == PERIPH_ID_NONE)
+		debug("ERROR: Peripheral ID %d not found\n", peripheral);
+
+	return &info[i];
+}
+
 static unsigned long exynos5_get_periph_rate(int peripheral)
 {
-	struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
-	unsigned long sclk, sub_clk;
-	unsigned int src, div, sub_div;
+	struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
+	unsigned long sclk = 0;
+	unsigned int src = 0, div = 0, sub_div = 0;
 	struct exynos5_clock *clk =
 			(struct exynos5_clock *)samsung_get_base_clock();
 
@@ -286,27 +389,30 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 		break;
 	case PERIPH_ID_I2S0:
 		src = readl(&clk->src_mau);
-		div = readl(&clk->div_mau);
+		div = sub_div = readl(&clk->div_mau);
 	case PERIPH_ID_SPI0:
 	case PERIPH_ID_SPI1:
 		src = readl(&clk->src_peric1);
-		div = readl(&clk->div_peric1);
+		div = sub_div = readl(&clk->div_peric1);
 		break;
 	case PERIPH_ID_SPI2:
 		src = readl(&clk->src_peric1);
-		div = readl(&clk->div_peric2);
+		div = sub_div = readl(&clk->div_peric2);
 		break;
 	case PERIPH_ID_SPI3:
 	case PERIPH_ID_SPI4:
 		src = readl(&clk->sclk_src_isp);
-		div = readl(&clk->sclk_div_isp);
+		div = sub_div = readl(&clk->sclk_div_isp);
 		break;
 	case PERIPH_ID_SDMMC0:
 	case PERIPH_ID_SDMMC1:
+		src = readl(&clk->src_fsys);
+		div = sub_div = readl(&clk->div_fsys1);
+		break;
 	case PERIPH_ID_SDMMC2:
 	case PERIPH_ID_SDMMC3:
 		src = readl(&clk->src_fsys);
-		div = readl(&clk->div_fsys1);
+		div = sub_div = readl(&clk->div_fsys2);
 		break;
 	case PERIPH_ID_I2C0:
 	case PERIPH_ID_I2C1:
@@ -316,18 +422,17 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 	case PERIPH_ID_I2C5:
 	case PERIPH_ID_I2C6:
 	case PERIPH_ID_I2C7:
-		sclk = exynos5_get_pll_clk(MPLL);
-		sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
-								& 0x7) + 1;
-		div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
-								& 0x7) + 1;
-		return (sclk / sub_div) / div;
+		src = EXYNOS_SRC_MPLL;
+		div = readl(&clk->div_top0);
+		sub_div = readl(&clk->div_top1);
+		break;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
 		return -1;
 	};
 
-	src = (src >> bit_info->src_bit) & 0xf;
+	if (bit_info->src_bit >= 0)
+		src = (src >> bit_info->src_bit) & bit_info->src_mask;
 
 	switch (src) {
 	case EXYNOS_SRC_MPLL:
@@ -340,68 +445,126 @@ static unsigned long exynos5_get_periph_rate(int peripheral)
 		sclk = exynos5_get_pll_clk(VPLL);
 		break;
 	default:
+		debug("%s: EXYNOS_SRC %d not supported\n", __func__, src);
 		return 0;
 	}
 
-	/* Ratio clock division for this peripheral */
-	sub_div = (div >> bit_info->div_bit) & 0xf;
-	sub_clk = sclk / (sub_div + 1);
-
-	/* Pre-ratio clock division for SDMMC0 and 2 */
-	if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
-		div = (div >> bit_info->prediv_bit) & 0xff;
-		return sub_clk / (div + 1);
-	}
+	/* Clock divider ratio for this peripheral */
+	if (bit_info->div_bit >= 0)
+		div = (div >> bit_info->div_bit) & bit_info->div_mask;
 
-	return sub_clk;
-}
+	/* Clock pre-divider ratio for this peripheral */
+	if (bit_info->prediv_bit >= 0)
+		sub_div = (sub_div >> bit_info->prediv_bit)
+			  & bit_info->prediv_mask;
 
-unsigned long clock_get_periph_rate(int peripheral)
-{
-	if (cpu_is_exynos5())
-		return exynos5_get_periph_rate(peripheral);
-	else
-		return 0;
+	/* Calculate and return required clock rate */
+	return (sclk / (div + 1)) / (sub_div + 1);
 }
 
-/* exynos5420: return pll clock frequency */
-static unsigned long exynos5420_get_pll_clk(int pllreg)
+static unsigned long exynos542x_get_periph_rate(int peripheral)
 {
+	struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
+	unsigned long sclk = 0;
+	unsigned int src = 0, div = 0, sub_div = 0;
 	struct exynos5420_clock *clk =
-		(struct exynos5420_clock *)samsung_get_base_clock();
-	unsigned long r, k = 0;
+			(struct exynos5420_clock *)samsung_get_base_clock();
 
-	switch (pllreg) {
-	case APLL:
-		r = readl(&clk->apll_con0);
+	switch (peripheral) {
+	case PERIPH_ID_UART0:
+	case PERIPH_ID_UART1:
+	case PERIPH_ID_UART2:
+	case PERIPH_ID_UART3:
+	case PERIPH_ID_PWM0:
+	case PERIPH_ID_PWM1:
+	case PERIPH_ID_PWM2:
+	case PERIPH_ID_PWM3:
+	case PERIPH_ID_PWM4:
+		src = readl(&clk->src_peric0);
+		div = readl(&clk->div_peric0);
 		break;
-	case MPLL:
-		r = readl(&clk->mpll_con0);
+	case PERIPH_ID_SPI0:
+	case PERIPH_ID_SPI1:
+	case PERIPH_ID_SPI2:
+		src = readl(&clk->src_peric1);
+		div = readl(&clk->div_peric1);
+		sub_div = readl(&clk->div_peric4);
 		break;
-	case EPLL:
-		r = readl(&clk->epll_con0);
-		k = readl(&clk->epll_con1);
+	case PERIPH_ID_SPI3:
+	case PERIPH_ID_SPI4:
+		src = readl(&clk->src_isp);
+		div = readl(&clk->div_isp1);
+		sub_div = readl(&clk->div_isp1);
 		break;
-	case VPLL:
-		r = readl(&clk->vpll_con0);
-		k = readl(&clk->vpll_con1);
+	case PERIPH_ID_SDMMC0:
+	case PERIPH_ID_SDMMC1:
+	case PERIPH_ID_SDMMC2:
+	case PERIPH_ID_SDMMC3:
+		src = readl(&clk->src_fsys);
+		div = readl(&clk->div_fsys1);
 		break;
-	case BPLL:
-		r = readl(&clk->bpll_con0);
+	case PERIPH_ID_I2C0:
+	case PERIPH_ID_I2C1:
+	case PERIPH_ID_I2C2:
+	case PERIPH_ID_I2C3:
+	case PERIPH_ID_I2C4:
+	case PERIPH_ID_I2C5:
+	case PERIPH_ID_I2C6:
+	case PERIPH_ID_I2C7:
+	case PERIPH_ID_I2C8:
+	case PERIPH_ID_I2C9:
+	case PERIPH_ID_I2C10:
+		src = EXYNOS542X_SRC_MPLL;
+		div = readl(&clk->div_top1);
 		break;
-	case RPLL:
-		r = readl(&clk->rpll_con0);
-		k = readl(&clk->rpll_con1);
+	default:
+		debug("%s: invalid peripheral %d", __func__, peripheral);
+		return -1;
+	};
+
+	if (bit_info->src_bit >= 0)
+		src = (src >> bit_info->src_bit) & bit_info->src_mask;
+
+	switch (src) {
+	case EXYNOS542X_SRC_MPLL:
+		sclk = exynos542x_get_pll_clk(MPLL);
 		break;
-	case SPLL:
-		r = readl(&clk->spll_con0);
+	case EXYNOS542X_SRC_SPLL:
+		sclk = exynos542x_get_pll_clk(SPLL);
+		break;
+	case EXYNOS542X_SRC_EPLL:
+		sclk = exynos542x_get_pll_clk(EPLL);
+		break;
+	case EXYNOS542X_SRC_RPLL:
+		sclk = exynos542x_get_pll_clk(RPLL);
 		break;
 	default:
-		printf("Unsupported PLL (%d)\n", pllreg);
+		debug("%s: EXYNOS542X_SRC %d not supported", __func__, src);
 		return 0;
 	}
 
-	return exynos_get_pll_clk(pllreg, r, k);
+	/* Clock divider ratio for this peripheral */
+	if (bit_info->div_bit >= 0)
+		div = (div >> bit_info->div_bit) & bit_info->div_mask;
+
+	/* Clock pre-divider ratio for this peripheral */
+	if (bit_info->prediv_bit >= 0)
+		sub_div = (sub_div >> bit_info->prediv_bit)
+			  & bit_info->prediv_mask;
+
+	/* Calculate and return required clock rate */
+	return (sclk / (div + 1)) / (sub_div + 1);
+}
+
+unsigned long clock_get_periph_rate(int peripheral)
+{
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420() || proid_is_exynos5800())
+			return exynos542x_get_periph_rate(peripheral);
+		return exynos5_get_periph_rate(peripheral);
+	} else {
+		return 0;
+	}
 }
 
 /* exynos4: return ARM clock frequency */
@@ -527,27 +690,6 @@ static unsigned long exynos4x12_get_pwm_clk(void)
 	return pclk;
 }
 
-/* exynos5420: return pwm clock frequency */
-static unsigned long exynos5420_get_pwm_clk(void)
-{
-	struct exynos5420_clock *clk =
-		(struct exynos5420_clock *)samsung_get_base_clock();
-	unsigned long pclk, sclk;
-	unsigned int ratio;
-
-	/*
-	 * CLK_DIV_PERIC0
-	 * PWM_RATIO [31:28]
-	 */
-	ratio = readl(&clk->div_peric0);
-	ratio = (ratio >> 28) & 0xf;
-	sclk = get_pll_clk(MPLL);
-
-	pclk = sclk / (ratio + 1);
-
-	return pclk;
-}
-
 /* exynos4: return uart clock frequency */
 static unsigned long exynos4_get_uart_clk(int dev_index)
 {
@@ -640,100 +782,6 @@ static unsigned long exynos4x12_get_uart_clk(int dev_index)
 	return uclk;
 }
 
-/* exynos5: return uart clock frequency */
-static unsigned long exynos5_get_uart_clk(int dev_index)
-{
-	struct exynos5_clock *clk =
-		(struct exynos5_clock *)samsung_get_base_clock();
-	unsigned long uclk, sclk;
-	unsigned int sel;
-	unsigned int ratio;
-
-	/*
-	 * CLK_SRC_PERIC0
-	 * UART0_SEL [3:0]
-	 * UART1_SEL [7:4]
-	 * UART2_SEL [8:11]
-	 * UART3_SEL [12:15]
-	 * UART4_SEL [16:19]
-	 * UART5_SEL [23:20]
-	 */
-	sel = readl(&clk->src_peric0);
-	sel = (sel >> (dev_index << 2)) & 0xf;
-
-	if (sel == 0x6)
-		sclk = get_pll_clk(MPLL);
-	else if (sel == 0x7)
-		sclk = get_pll_clk(EPLL);
-	else if (sel == 0x8)
-		sclk = get_pll_clk(VPLL);
-	else
-		return 0;
-
-	/*
-	 * CLK_DIV_PERIC0
-	 * UART0_RATIO [3:0]
-	 * UART1_RATIO [7:4]
-	 * UART2_RATIO [8:11]
-	 * UART3_RATIO [12:15]
-	 * UART4_RATIO [16:19]
-	 * UART5_RATIO [23:20]
-	 */
-	ratio = readl(&clk->div_peric0);
-	ratio = (ratio >> (dev_index << 2)) & 0xf;
-
-	uclk = sclk / (ratio + 1);
-
-	return uclk;
-}
-
-/* exynos5420: return uart clock frequency */
-static unsigned long exynos5420_get_uart_clk(int dev_index)
-{
-	struct exynos5420_clock *clk =
-		(struct exynos5420_clock *)samsung_get_base_clock();
-	unsigned long uclk, sclk;
-	unsigned int sel;
-	unsigned int ratio;
-
-	/*
-	 * CLK_SRC_PERIC0
-	 * UART0_SEL [6:4]
-	 * UART1_SEL [10:8]
-	 * UART2_SEL [14:12]
-	 * UART3_SEL [18:16]
-	 * generalised calculation as follows
-	 * sel = (sel >> ((dev_index * 4) + 4)) & mask;
-	 */
-	sel = readl(&clk->src_peric0);
-	sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
-
-	if (sel == 0x3)
-		sclk = get_pll_clk(MPLL);
-	else if (sel == 0x6)
-		sclk = get_pll_clk(EPLL);
-	else if (sel == 0x7)
-		sclk = get_pll_clk(RPLL);
-	else
-		return 0;
-
-	/*
-	 * CLK_DIV_PERIC0
-	 * UART0_RATIO [11:8]
-	 * UART1_RATIO [15:12]
-	 * UART2_RATIO [19:16]
-	 * UART3_RATIO [23:20]
-	 * generalised calculation as follows
-	 * ratio = (ratio >> ((dev_index * 4) + 8)) & mask;
-	 */
-	ratio = readl(&clk->div_peric0);
-	ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
-
-	uclk = sclk / (ratio + 1);
-
-	return uclk;
-}
-
 static unsigned long exynos4_get_mmc_clk(int dev_index)
 {
 	struct exynos4_clock *clk =
@@ -783,94 +831,6 @@ static unsigned long exynos4_get_mmc_clk(int dev_index)
 	return uclk;
 }
 
-static unsigned long exynos5_get_mmc_clk(int dev_index)
-{
-	struct exynos5_clock *clk =
-		(struct exynos5_clock *)samsung_get_base_clock();
-	unsigned long uclk, sclk;
-	unsigned int sel, ratio, pre_ratio;
-	int shift = 0;
-
-	sel = readl(&clk->src_fsys);
-	sel = (sel >> (dev_index << 2)) & 0xf;
-
-	if (sel == 0x6)
-		sclk = get_pll_clk(MPLL);
-	else if (sel == 0x7)
-		sclk = get_pll_clk(EPLL);
-	else if (sel == 0x8)
-		sclk = get_pll_clk(VPLL);
-	else
-		return 0;
-
-	switch (dev_index) {
-	case 0:
-	case 1:
-		ratio = readl(&clk->div_fsys1);
-		pre_ratio = readl(&clk->div_fsys1);
-		break;
-	case 2:
-	case 3:
-		ratio = readl(&clk->div_fsys2);
-		pre_ratio = readl(&clk->div_fsys2);
-		break;
-	default:
-		return 0;
-	}
-
-	if (dev_index == 1 || dev_index == 3)
-		shift = 16;
-
-	ratio = (ratio >> shift) & 0xf;
-	pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
-	uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
-
-	return uclk;
-}
-
-static unsigned long exynos5420_get_mmc_clk(int dev_index)
-{
-	struct exynos5420_clock *clk =
-		(struct exynos5420_clock *)samsung_get_base_clock();
-	unsigned long uclk, sclk;
-	unsigned int sel, ratio;
-
-	/*
-	 * CLK_SRC_FSYS
-	 * MMC0_SEL [10:8]
-	 * MMC1_SEL [14:12]
-	 * MMC2_SEL [18:16]
-	 * generalised calculation as follows
-	 * sel = (sel >> ((dev_index * 4) + 8)) & mask
-	 */
-	sel = readl(&clk->src_fsys);
-	sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
-
-	if (sel == 0x3)
-		sclk = get_pll_clk(MPLL);
-	else if (sel == 0x4)
-		sclk = get_pll_clk(SPLL);
-	else if (sel == 0x6)
-		sclk = get_pll_clk(EPLL);
-	else
-		return 0;
-
-	/*
-	 * CLK_DIV_FSYS1
-	 * MMC0_RATIO [9:0]
-	 * MMC1_RATIO [19:10]
-	 * MMC2_RATIO [29:20]
-	 * generalised calculation as follows
-	 * ratio = (ratio >> (dev_index * 10)) & mask
-	 */
-	ratio = readl(&clk->div_fsys1);
-	ratio = (ratio >> (dev_index * 10)) & 0x3ff;
-
-	uclk = (sclk / (ratio + 1));
-
-	return uclk;
-}
-
 /* exynos4: set the mmc clock */
 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 {
@@ -1249,29 +1209,6 @@ void exynos4_set_mipi_clk(void)
 	clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
 }
 
-/*
- * I2C
- *
- * exynos5: obtaining the I2C clock
- */
-static unsigned long exynos5_get_i2c_clk(void)
-{
-	struct exynos5_clock *clk =
-		(struct exynos5_clock *)samsung_get_base_clock();
-	unsigned long aclk_66, aclk_66_pre, sclk;
-	unsigned int ratio;
-
-	sclk = get_pll_clk(MPLL);
-
-	ratio = (readl(&clk->div_top1)) >> 24;
-	ratio &= 0x7;
-	aclk_66_pre = sclk / (ratio + 1);
-	ratio = readl(&clk->div_top0);
-	ratio &= 0x7;
-	aclk_66 = aclk_66_pre / (ratio + 1);
-	return aclk_66;
-}
-
 int exynos5_set_epll_clk(unsigned long rate)
 {
 	unsigned int epll_con, epll_con_k;
@@ -1585,7 +1522,7 @@ unsigned long get_pll_clk(int pllreg)
 {
 	if (cpu_is_exynos5()) {
 		if (proid_is_exynos5420() || proid_is_exynos5800())
-			return exynos5420_get_pll_clk(pllreg);
+			return exynos542x_get_pll_clk(pllreg);
 		return exynos5_get_pll_clk(pllreg);
 	} else {
 		if (proid_is_exynos4412())
@@ -1608,7 +1545,7 @@ unsigned long get_arm_clk(void)
 unsigned long get_i2c_clk(void)
 {
 	if (cpu_is_exynos5()) {
-		return exynos5_get_i2c_clk();
+		return clock_get_periph_rate(PERIPH_ID_I2C0);
 	} else if (cpu_is_exynos4()) {
 		return exynos4_get_i2c_clk();
 	} else {
@@ -1620,8 +1557,6 @@ unsigned long get_i2c_clk(void)
 unsigned long get_pwm_clk(void)
 {
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
-			return exynos5420_get_pwm_clk();
 		return clock_get_periph_rate(PERIPH_ID_PWM0);
 	} else {
 		if (proid_is_exynos4412())
@@ -1632,10 +1567,28 @@ unsigned long get_pwm_clk(void)
 
 unsigned long get_uart_clk(int dev_index)
 {
+	enum periph_id id;
+
+	switch (dev_index) {
+	case 0:
+		id = PERIPH_ID_UART0;
+		break;
+	case 1:
+		id = PERIPH_ID_UART1;
+		break;
+	case 2:
+		id = PERIPH_ID_UART2;
+		break;
+	case 3:
+		id = PERIPH_ID_UART3;
+		break;
+	default:
+		debug("%s: invalid UART index %d", __func__, dev_index);
+		return -1;
+	}
+
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
-			return exynos5420_get_uart_clk(dev_index);
-		return exynos5_get_uart_clk(dev_index);
+		return clock_get_periph_rate(id);
 	} else {
 		if (proid_is_exynos4412())
 			return exynos4x12_get_uart_clk(dev_index);
@@ -1645,10 +1598,28 @@ unsigned long get_uart_clk(int dev_index)
 
 unsigned long get_mmc_clk(int dev_index)
 {
+	enum periph_id id;
+
+	switch (dev_index) {
+	case 0:
+		id = PERIPH_ID_SDMMC0;
+		break;
+	case 1:
+		id = PERIPH_ID_SDMMC1;
+		break;
+	case 2:
+		id = PERIPH_ID_SDMMC2;
+		break;
+	case 3:
+		id = PERIPH_ID_SDMMC3;
+		break;
+	default:
+		debug("%s: invalid MMC index %d", __func__, dev_index);
+		return -1;
+	}
+
 	if (cpu_is_exynos5()) {
-		if (proid_is_exynos5420() || proid_is_exynos5800())
-			return exynos5420_get_mmc_clk(dev_index);
-		return exynos5_get_mmc_clk(dev_index);
+		return clock_get_periph_rate(id);
 	} else {
 		return exynos4_get_mmc_clk(dev_index);
 	}
@@ -1656,6 +1627,10 @@ unsigned long get_mmc_clk(int dev_index)
 
 void set_mmc_clk(int dev_index, unsigned int div)
 {
+	/* If want to set correct value, it needs to substract one from div.*/
+	if (div > 0)
+		div -= 1;
+
 	if (cpu_is_exynos5()) {
 		if (proid_is_exynos5420() || proid_is_exynos5800())
 			exynos5420_set_mmc_clk(dev_index, div);
diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
index 1520d642c5..1b12051656 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -102,10 +102,34 @@ static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
 	}
 }
 
+static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable)
+{
+	struct exynos5420_power *power =
+		(struct exynos5420_power *)samsung_get_base_power();
+
+	if (enable) {
+		/* Enabling USBDEV_PHY */
+		setbits_le32(&power->usbdev_phy_control,
+				POWER_USB_DRD_PHY_CTRL_EN);
+		setbits_le32(&power->usbdev1_phy_control,
+				POWER_USB_DRD_PHY_CTRL_EN);
+	} else {
+		/* Disabling USBDEV_PHY */
+		clrbits_le32(&power->usbdev_phy_control,
+				POWER_USB_DRD_PHY_CTRL_EN);
+		clrbits_le32(&power->usbdev1_phy_control,
+				POWER_USB_DRD_PHY_CTRL_EN);
+	}
+}
+
 void set_usbdrd_phy_ctrl(unsigned int enable)
 {
-	if (cpu_is_exynos5())
-		exynos5_set_usbdrd_phy_ctrl(enable);
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420() || proid_is_exynos5800())
+			exynos5420_set_usbdev_phy_ctrl(enable);
+		else
+			exynos5_set_usbdrd_phy_ctrl(enable);
+	}
 }
 
 static void exynos5_dp_phy_control(unsigned int enable)
diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c
index bc237c969f..c7f943eb6a 100644
--- a/arch/arm/cpu/armv7/exynos/spl_boot.c
+++ b/arch/arm/cpu/armv7/exynos/spl_boot.c
@@ -309,4 +309,3 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	while (1)
 		;
 }
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
diff --git a/arch/arm/cpu/armv7/highbank/Kconfig b/arch/arm/cpu/armv7/highbank/Kconfig
deleted file mode 100644
index 0e73c04142..0000000000
--- a/arch/arm/cpu/armv7/highbank/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if ARCH_HIGHBANK
-
-config SYS_BOARD
-	default "highbank"
-
-config SYS_SOC
-	default "highbank"
-
-config SYS_CONFIG_NAME
-	default "highbank"
-
-endif
diff --git a/arch/arm/cpu/armv7/highbank/Makefile b/arch/arm/cpu/armv7/highbank/Makefile
deleted file mode 100644
index 876099d9a1..0000000000
--- a/arch/arm/cpu/armv7/highbank/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= timer.o
diff --git a/arch/arm/cpu/armv7/highbank/timer.c b/arch/arm/cpu/armv7/highbank/timer.c
deleted file mode 100644
index d56bf21133..0000000000
--- a/arch/arm/cpu/armv7/highbank/timer.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2010-2011 Calxeda, Inc.
- *
- * Based on arm926ejs/mx27/timer.c
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch-armv7/systimer.h>
-
-#undef SYSTIMER_BASE
-#define SYSTIMER_BASE		0xFFF34000	/* Timer 0 and 1 base	*/
-
-static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
-
-/*
- * Start the timer
- */
-int timer_init(void)
-{
-	/*
-	 * Setup timer0
-	 */
-	writel(0, &systimer_base->timer0control);
-	writel(SYSTIMER_RELOAD, &systimer_base->timer0load);
-	writel(SYSTIMER_RELOAD, &systimer_base->timer0value);
-	writel(SYSTIMER_EN | SYSTIMER_32BIT | SYSTIMER_PRESC_256,
-		&systimer_base->timer0control);
-
-	return 0;
-
-}
diff --git a/arch/arm/cpu/armv7/keystone/Kconfig b/arch/arm/cpu/armv7/keystone/Kconfig
deleted file mode 100644
index 134ae87fe1..0000000000
--- a/arch/arm/cpu/armv7/keystone/Kconfig
+++ /dev/null
@@ -1,22 +0,0 @@
-if ARCH_KEYSTONE
-
-choice
-	prompt "TI Keystone board select"
-
-config TARGET_K2HK_EVM
-	bool "TI Keystone 2 Kepler/Hawking EVM"
-
-config TARGET_K2E_EVM
-	bool "TI Keystone 2 Edison EVM"
-
-config TARGET_K2L_EVM
-	bool "TI Keystone 2 Lamar EVM"
-
-endchoice
-
-config SYS_SOC
-	default "keystone"
-
-source "board/ti/ks2_evm/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile
deleted file mode 100644
index ed030db2c8..0000000000
--- a/arch/arm/cpu/armv7/keystone/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# (C) Copyright 2012-2014
-#     Texas Instruments Incorporated, <www.ti.com>
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y	+= init.o
-obj-y	+= psc.o
-obj-y	+= clock.o
-obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
-obj-$(CONFIG_SOC_K2E) += clock-k2e.o
-obj-$(CONFIG_SOC_K2L) += clock-k2l.o
-obj-y	+= cmd_clock.o
-obj-y	+= cmd_mon.o
-obj-y	+= msmc.o
-obj-y	+= ddr3.o cmd_ddr3.o
-obj-y	+= keystone.o
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c
deleted file mode 100644
index 31f66613ef..0000000000
--- a/arch/arm/cpu/armv7/keystone/clock-k2e.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Keystone2: get clk rate for K2E
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clock_defs.h>
-
-const struct keystone_pll_regs keystone_pll_regs[] = {
-	[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
-	[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
-	[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
-int dev_speeds[] = {
-	SPD800,
-	SPD850,
-	SPD1000,
-	SPD1250,
-	SPD1350,
-	SPD1400,
-	SPD1500,
-	SPD1400,
-	SPD1350,
-	SPD1250,
-	SPD1000,
-	SPD850,
-	SPD800
-};
-
-/**
- * pll_freq_get - get pll frequency
- * Fout = Fref * NF(mult) / NR(prediv) / OD
- * @pll:	pll identifier
- */
-static unsigned long pll_freq_get(int pll)
-{
-	unsigned long mult = 1, prediv = 1, output_div = 2;
-	unsigned long ret;
-	u32 tmp, reg;
-
-	if (pll == CORE_PLL) {
-		ret = external_clk[sys_clk];
-		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
-			/* PLL mode */
-			tmp = __raw_readl(KS2_MAINPLLCTL0);
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
-				(pllctl_reg_read(pll, mult) &
-				PLLM_MULT_LO_MASK)) + 1;
-			output_div = ((pllctl_reg_read(pll, secctl) >>
-				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
-			ret = ret / prediv / output_div * mult;
-		}
-	} else {
-		switch (pll) {
-		case PASS_PLL:
-			ret = external_clk[pa_clk];
-			reg = KS2_PASSPLLCTL0;
-			break;
-		case DDR3_PLL:
-			ret = external_clk[ddr3_clk];
-			reg = KS2_DDR3APLLCTL0;
-			break;
-		default:
-			return 0;
-		}
-
-		tmp = __raw_readl(reg);
-
-		if (!(tmp & PLLCTL_BYPASS)) {
-			/* Bypass disabled */
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
-			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
-				      PLL_CLKOD_MASK) + 1;
-			ret = ((ret / prediv) * mult) / output_div;
-		}
-	}
-
-	return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
-	switch (clk) {
-	case core_pll_clk:      return pll_freq_get(CORE_PLL);
-	case pass_pll_clk:      return pll_freq_get(PASS_PLL);
-	case ddr3_pll_clk:      return pll_freq_get(DDR3_PLL);
-	case sys_clk0_1_clk:
-	case sys_clk0_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(1);
-	case sys_clk1_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(2);
-	case sys_clk2_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(3);
-	case sys_clk3_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(4);
-	case sys_clk0_2_clk:    return clk_get_rate(sys_clk0_clk) / 2;
-	case sys_clk0_3_clk:    return clk_get_rate(sys_clk0_clk) / 3;
-	case sys_clk0_4_clk:    return clk_get_rate(sys_clk0_clk) / 4;
-	case sys_clk0_6_clk:    return clk_get_rate(sys_clk0_clk) / 6;
-	case sys_clk0_8_clk:    return clk_get_rate(sys_clk0_clk) / 8;
-	case sys_clk0_12_clk:   return clk_get_rate(sys_clk0_clk) / 12;
-	case sys_clk0_24_clk:   return clk_get_rate(sys_clk0_clk) / 24;
-	case sys_clk1_3_clk:    return clk_get_rate(sys_clk1_clk) / 3;
-	case sys_clk1_4_clk:    return clk_get_rate(sys_clk1_clk) / 4;
-	case sys_clk1_6_clk:    return clk_get_rate(sys_clk1_clk) / 6;
-	case sys_clk1_12_clk:   return clk_get_rate(sys_clk1_clk) / 12;
-	default:
-		break;
-	}
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2hk.c b/arch/arm/cpu/armv7/keystone/clock-k2hk.c
deleted file mode 100644
index 1591960795..0000000000
--- a/arch/arm/cpu/armv7/keystone/clock-k2hk.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Keystone2: get clk rate for K2HK
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clock_defs.h>
-
-const struct keystone_pll_regs keystone_pll_regs[] = {
-	[CORE_PLL]	= {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
-	[PASS_PLL]	= {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
-	[TETRIS_PLL]	= {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
-	[DDR3A_PLL]	= {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-	[DDR3B_PLL]	= {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
-};
-
-int dev_speeds[] = {
-	SPD800,
-	SPD1000,
-	SPD1200,
-	SPD800,
-	SPD800,
-	SPD800,
-	SPD800,
-	SPD800,
-	SPD1200,
-	SPD1000,
-	SPD800,
-	SPD800,
-	SPD800,
-};
-
-int arm_speeds[] = {
-	SPD800,
-	SPD1000,
-	SPD1200,
-	SPD1350,
-	SPD1400,
-	SPD800,
-	SPD1400,
-	SPD1350,
-	SPD1200,
-	SPD1000,
-	SPD800,
-	SPD800,
-	SPD800,
-};
-
-/**
- * pll_freq_get - get pll frequency
- * Fout = Fref * NF(mult) / NR(prediv) / OD
- * @pll:	pll identifier
- */
-static unsigned long pll_freq_get(int pll)
-{
-	unsigned long mult = 1, prediv = 1, output_div = 2;
-	unsigned long ret;
-	u32 tmp, reg;
-
-	if (pll == CORE_PLL) {
-		ret = external_clk[sys_clk];
-		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
-			/* PLL mode */
-			tmp = __raw_readl(KS2_MAINPLLCTL0);
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
-				(pllctl_reg_read(pll, mult) &
-				 PLLM_MULT_LO_MASK)) + 1;
-			output_div = ((pllctl_reg_read(pll, secctl) >>
-				       PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
-			ret = ret / prediv / output_div * mult;
-		}
-	} else {
-		switch (pll) {
-		case PASS_PLL:
-			ret = external_clk[pa_clk];
-			reg = KS2_PASSPLLCTL0;
-			break;
-		case TETRIS_PLL:
-			ret = external_clk[tetris_clk];
-			reg = KS2_ARMPLLCTL0;
-			break;
-		case DDR3A_PLL:
-			ret = external_clk[ddr3a_clk];
-			reg = KS2_DDR3APLLCTL0;
-			break;
-		case DDR3B_PLL:
-			ret = external_clk[ddr3b_clk];
-			reg = KS2_DDR3BPLLCTL0;
-			break;
-		default:
-			return 0;
-		}
-
-		tmp = __raw_readl(reg);
-
-		if (!(tmp & PLLCTL_BYPASS)) {
-			/* Bypass disabled */
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
-			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
-				      PLL_CLKOD_MASK) + 1;
-			ret = ((ret / prediv) * mult) / output_div;
-		}
-	}
-
-	return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
-	switch (clk) {
-	case core_pll_clk:	return pll_freq_get(CORE_PLL);
-	case pass_pll_clk:	return pll_freq_get(PASS_PLL);
-	case tetris_pll_clk:	return pll_freq_get(TETRIS_PLL);
-	case ddr3a_pll_clk:	return pll_freq_get(DDR3A_PLL);
-	case ddr3b_pll_clk:	return pll_freq_get(DDR3B_PLL);
-	case sys_clk0_1_clk:
-	case sys_clk0_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(1);
-	case sys_clk1_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(2);
-	case sys_clk2_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(3);
-	case sys_clk3_clk:	return pll_freq_get(CORE_PLL) / pll0div_read(4);
-	case sys_clk0_2_clk:	return clk_get_rate(sys_clk0_clk) / 2;
-	case sys_clk0_3_clk:	return clk_get_rate(sys_clk0_clk) / 3;
-	case sys_clk0_4_clk:	return clk_get_rate(sys_clk0_clk) / 4;
-	case sys_clk0_6_clk:	return clk_get_rate(sys_clk0_clk) / 6;
-	case sys_clk0_8_clk:	return clk_get_rate(sys_clk0_clk) / 8;
-	case sys_clk0_12_clk:	return clk_get_rate(sys_clk0_clk) / 12;
-	case sys_clk0_24_clk:	return clk_get_rate(sys_clk0_clk) / 24;
-	case sys_clk1_3_clk:	return clk_get_rate(sys_clk1_clk) / 3;
-	case sys_clk1_4_clk:	return clk_get_rate(sys_clk1_clk) / 4;
-	case sys_clk1_6_clk:	return clk_get_rate(sys_clk1_clk) / 6;
-	case sys_clk1_12_clk:	return clk_get_rate(sys_clk1_clk) / 12;
-	default:
-		break;
-	}
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/keystone/clock-k2l.c b/arch/arm/cpu/armv7/keystone/clock-k2l.c
deleted file mode 100644
index 1c5e4d54d8..0000000000
--- a/arch/arm/cpu/armv7/keystone/clock-k2l.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Keystone2: get clk rate for K2L
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clock_defs.h>
-
-const struct keystone_pll_regs keystone_pll_regs[] = {
-	[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
-	[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
-	[TETRIS_PLL] = {KS2_ARMPLLCTL0,  KS2_ARMPLLCTL1},
-	[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
-};
-
-int dev_speeds[] = {
-	SPD800,
-	SPD1000,
-	SPD1200,
-	SPD800,
-	SPD800,
-	SPD800,
-	SPD800,
-	SPD800,
-	SPD1200,
-	SPD1000,
-	SPD800,
-	SPD800,
-	SPD800,
-};
-
-int arm_speeds[] = {
-	SPD800,
-	SPD1000,
-	SPD1200,
-	SPD1350,
-	SPD1400,
-	SPD800,
-	SPD1400,
-	SPD1350,
-	SPD1200,
-	SPD1000,
-	SPD800,
-	SPD800,
-	SPD800,
-};
-
-/**
- * pll_freq_get - get pll frequency
- * Fout = Fref * NF(mult) / NR(prediv) / OD
- * @pll:	pll identifier
- */
-static unsigned long pll_freq_get(int pll)
-{
-	unsigned long mult = 1, prediv = 1, output_div = 2;
-	unsigned long ret;
-	u32 tmp, reg;
-
-	if (pll == CORE_PLL) {
-		ret = external_clk[sys_clk];
-		if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
-			/* PLL mode */
-			tmp = __raw_readl(KS2_MAINPLLCTL0);
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
-				(pllctl_reg_read(pll, mult) &
-				PLLM_MULT_LO_MASK)) + 1;
-			output_div = ((pllctl_reg_read(pll, secctl) >>
-					PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
-
-			ret = ret / prediv / output_div * mult;
-		}
-	} else {
-		switch (pll) {
-		case PASS_PLL:
-			ret = external_clk[pa_clk];
-			reg = KS2_PASSPLLCTL0;
-			break;
-		case TETRIS_PLL:
-			ret = external_clk[tetris_clk];
-			reg = KS2_ARMPLLCTL0;
-			break;
-		case DDR3_PLL:
-			ret = external_clk[ddr3_clk];
-			reg = KS2_DDR3APLLCTL0;
-			break;
-		default:
-			return 0;
-		}
-
-		tmp = __raw_readl(reg);
-		if (!(tmp & PLLCTL_BYPASS)) {
-			/* Bypass disabled */
-			prediv = (tmp & PLL_DIV_MASK) + 1;
-			mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
-			output_div = ((tmp >> PLL_CLKOD_SHIFT) &
-				      PLL_CLKOD_MASK) + 1;
-			ret = ((ret / prediv) * mult) / output_div;
-		}
-	}
-
-	return ret;
-}
-
-unsigned long clk_get_rate(unsigned int clk)
-{
-	switch (clk) {
-	case core_pll_clk:      return pll_freq_get(CORE_PLL);
-	case pass_pll_clk:      return pll_freq_get(PASS_PLL);
-	case tetris_pll_clk:    return pll_freq_get(TETRIS_PLL);
-	case ddr3_pll_clk:      return pll_freq_get(DDR3_PLL);
-	case sys_clk0_1_clk:
-	case sys_clk0_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(1);
-	case sys_clk1_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(2);
-	case sys_clk2_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(3);
-	case sys_clk3_clk:      return pll_freq_get(CORE_PLL) / pll0div_read(4);
-	case sys_clk0_2_clk:    return clk_get_rate(sys_clk0_clk) / 2;
-	case sys_clk0_3_clk:    return clk_get_rate(sys_clk0_clk) / 3;
-	case sys_clk0_4_clk:    return clk_get_rate(sys_clk0_clk) / 4;
-	case sys_clk0_6_clk:    return clk_get_rate(sys_clk0_clk) / 6;
-	case sys_clk0_8_clk:    return clk_get_rate(sys_clk0_clk) / 8;
-	case sys_clk0_12_clk:   return clk_get_rate(sys_clk0_clk) / 12;
-	case sys_clk0_24_clk:   return clk_get_rate(sys_clk0_clk) / 24;
-	case sys_clk1_3_clk:    return clk_get_rate(sys_clk1_clk) / 3;
-	case sys_clk1_4_clk:    return clk_get_rate(sys_clk1_clk) / 4;
-	case sys_clk1_6_clk:    return clk_get_rate(sys_clk1_clk) / 6;
-	case sys_clk1_12_clk:   return clk_get_rate(sys_clk1_clk) / 12;
-	default:
-		break;
-	}
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
deleted file mode 100644
index d13fbc1a4b..0000000000
--- a/arch/arm/cpu/armv7/keystone/clock.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Keystone2: pll initialization
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clock_defs.h>
-
-#define MAX_SPEEDS		13
-
-static void wait_for_completion(const struct pll_init_data *data)
-{
-	int i;
-	for (i = 0; i < 100; i++) {
-		sdelay(450);
-		if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0)
-			break;
-	}
-}
-
-void init_pll(const struct pll_init_data *data)
-{
-	u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj;
-
-	pllm = data->pll_m - 1;
-	plld = (data->pll_d - 1) & PLL_DIV_MASK;
-	pllod = (data->pll_od - 1) & PLL_CLKOD_MASK;
-
-	if (data->pll == MAIN_PLL) {
-		/* The requered delay before main PLL configuration */
-		sdelay(210000);
-
-		tmp = pllctl_reg_read(data->pll, secctl);
-
-		if (tmp & (PLLCTL_BYPASS)) {
-			setbits_le32(keystone_pll_regs[data->pll].reg1,
-				     BIT(MAIN_ENSAT_OFFSET));
-
-			pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
-					   PLLCTL_PLLENSRC);
-			sdelay(340);
-
-			pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS);
-			pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN);
-			sdelay(21000);
-
-			pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN);
-		} else {
-			pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN |
-					   PLLCTL_PLLENSRC);
-			sdelay(340);
-		}
-
-		pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
-
-		clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
-				PLLM_MULT_HI_SMASK, (pllm << 6));
-
-		/* Set the BWADJ     (12 bit field)  */
-		tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */
-		clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
-				PLL_BWADJ_LO_SMASK,
-				(tmp_ctl << PLL_BWADJ_LO_SHIFT));
-		clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
-				PLL_BWADJ_HI_MASK,
-				(tmp_ctl >> 8));
-
-		/*
-		 * Set the pll divider (6 bit field) *
-		 * PLLD[5:0] is located in MAINPLLCTL0
-		 */
-		clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
-				PLL_DIV_MASK, plld);
-
-		/* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */
-		pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK,
-			       (pllod << PLL_CLKOD_SHIFT));
-		wait_for_completion(data);
-
-		pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1);
-		pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2);
-		pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3);
-		pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4);
-		pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5);
-
-		pllctl_reg_setbits(data->pll, alnctl, 0x1f);
-
-		/*
-		 * Set GOSET bit in PLLCMD to initiate the GO operation
-		 * to change the divide
-		 */
-		pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO);
-		sdelay(1500); /* wait for the phase adj */
-		wait_for_completion(data);
-
-		/* Reset PLL */
-		pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST);
-		sdelay(21000);	/* Wait for a minimum of 7 us*/
-		pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST);
-		sdelay(105000);	/* Wait for PLL Lock time (min 50 us) */
-
-		pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS);
-
-		tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
-
-#ifndef CONFIG_SOC_K2E
-	} else if (data->pll == TETRIS_PLL) {
-		bwadj = pllm >> 1;
-		/* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
-		setbits_le32(keystone_pll_regs[data->pll].reg0,  PLLCTL_BYPASS);
-		/*
-		 * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass)
-		 * only applicable for Kepler
-		 */
-		clrbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
-		/* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */
-		setbits_le32(keystone_pll_regs[data->pll].reg1 ,
-			     PLL_PLLRST | PLLCTL_ENSAT);
-
-		/*
-		 * 3 Program PLLM and PLLD in PLLCTL0 register
-		 * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in
-		 * PLLCTL1 register. BWADJ value must be set
-		 * to ((PLLM + 1) >> 1) – 1)
-		 */
-		tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
-			(pllm << 6) |
-			(plld & PLL_DIV_MASK) |
-			(pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS;
-		__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
-
-		/* Set BWADJ[11:8] bits */
-		tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
-		tmp &= ~(PLL_BWADJ_HI_MASK);
-		tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK);
-		__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
-		/*
-		 * 5 Wait for at least 5 us based on the reference
-		 * clock (PLL reset time)
-		 */
-		sdelay(21000);	/* Wait for a minimum of 7 us*/
-
-		/* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */
-		clrbits_le32(keystone_pll_regs[data->pll].reg1, PLL_PLLRST);
-		/*
-		 * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1)
-		 * (PLL lock time)
-		 */
-		sdelay(105000);
-		/* 8 disable bypass */
-		clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
-		/*
-		 * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass)
-		 * only applicable for Kepler
-		 */
-		setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
-#endif
-	} else {
-		setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
-		/*
-		 * process keeps state of Bypass bit while programming
-		 * all other DDR PLL settings
-		 */
-		tmp = __raw_readl(keystone_pll_regs[data->pll].reg0);
-		tmp &= PLLCTL_BYPASS;	/* clear everything except Bypass */
-
-		/*
-		 * Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0,
-		 * bypass disabled
-		 */
-		bwadj = pllm >> 1;
-		tmp |= ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) |
-			(pllm << PLL_MULT_SHIFT) |
-			(plld & PLL_DIV_MASK) |
-			(pllod << PLL_CLKOD_SHIFT);
-		__raw_writel(tmp, keystone_pll_regs[data->pll].reg0);
-
-		/* Set BWADJ[11:8] bits */
-		tmp = __raw_readl(keystone_pll_regs[data->pll].reg1);
-		tmp &= ~(PLL_BWADJ_HI_MASK);
-		tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
-
-		__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
-
-		/* Reset bit: bit 14 for both DDR3 & PASS PLL */
-		tmp = PLL_PLLRST;
-		/* Set RESET bit = 1 */
-		setbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
-		/* Wait for a minimum of 7 us*/
-		sdelay(21000);
-		/* Clear RESET bit */
-		clrbits_le32(keystone_pll_regs[data->pll].reg1, tmp);
-		sdelay(105000);
-
-		/* clear BYPASS (Enable PLL Mode) */
-		clrbits_le32(keystone_pll_regs[data->pll].reg0, PLLCTL_BYPASS);
-		sdelay(21000);	/* Wait for a minimum of 7 us*/
-	}
-
-	/*
-	 * This is required to provide a delay between multiple
-	 * consequent PPL configurations
-	 */
-	sdelay(210000);
-}
-
-void init_plls(int num_pll, struct pll_init_data *config)
-{
-	int i;
-
-	for (i = 0; i < num_pll; i++)
-		init_pll(&config[i]);
-}
-
-static int get_max_speed(u32 val, int *speeds)
-{
-	int j;
-
-	if (!val)
-		return speeds[0];
-
-	for (j = 1; j < MAX_SPEEDS; j++) {
-		if (val == 1)
-			return speeds[j];
-		val >>= 1;
-	}
-
-	return SPD800;
-}
-
-#ifdef CONFIG_SOC_K2HK
-static u32 read_efuse_bootrom(void)
-{
-	return (cpu_revision() > 1) ? __raw_readl(KS2_EFUSE_BOOTROM) :
-		__raw_readl(KS2_REV1_DEVSPEED);
-}
-#else
-static inline u32 read_efuse_bootrom(void)
-{
-	return __raw_readl(KS2_EFUSE_BOOTROM);
-}
-#endif
-
-inline int get_max_dev_speed(void)
-{
-	return get_max_speed(read_efuse_bootrom() & 0xffff, dev_speeds);
-}
-
-#ifndef CONFIG_SOC_K2E
-inline int get_max_arm_speed(void)
-{
-	return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
-}
-#endif
-
-void pass_pll_pa_clk_enable(void)
-{
-	u32 reg;
-
-	reg = readl(keystone_pll_regs[PASS_PLL].reg1);
-
-	reg |= PLLCTL_PAPLL;
-	writel(reg, keystone_pll_regs[PASS_PLL].reg1);
-
-	/* wait till clock is enabled */
-	sdelay(15000);
-}
diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
deleted file mode 100644
index af1b701e82..0000000000
--- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * keystone2: commands for clocks
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/psc_defs.h>
-
-struct pll_init_data cmd_pll_data = {
-	.pll = MAIN_PLL,
-	.pll_m = 16,
-	.pll_d = 1,
-	.pll_od = 2,
-};
-
-int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	if (argc != 5)
-		goto pll_cmd_usage;
-
-	if (strncmp(argv[1], "pa", 2) == 0)
-		cmd_pll_data.pll = PASS_PLL;
-#ifndef CONFIG_SOC_K2E
-	else if (strncmp(argv[1], "arm", 3) == 0)
-		cmd_pll_data.pll = TETRIS_PLL;
-#endif
-#ifdef CONFIG_SOC_K2HK
-	else if (strncmp(argv[1], "ddr3a", 5) == 0)
-		cmd_pll_data.pll = DDR3A_PLL;
-	else if (strncmp(argv[1], "ddr3b", 5) == 0)
-		cmd_pll_data.pll = DDR3B_PLL;
-#else
-	else if (strncmp(argv[1], "ddr3", 4) == 0)
-		cmd_pll_data.pll = DDR3_PLL;
-#endif
-	else
-		goto pll_cmd_usage;
-
-	cmd_pll_data.pll_m   = simple_strtoul(argv[2], NULL, 10);
-	cmd_pll_data.pll_d   = simple_strtoul(argv[3], NULL, 10);
-	cmd_pll_data.pll_od  = simple_strtoul(argv[4], NULL, 10);
-
-	printf("Trying to set pll %d; mult %d; div %d; OD %d\n",
-	       cmd_pll_data.pll, cmd_pll_data.pll_m,
-	       cmd_pll_data.pll_d, cmd_pll_data.pll_od);
-	init_pll(&cmd_pll_data);
-
-	return 0;
-
-pll_cmd_usage:
-	return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
-	pllset, 5,      0,      do_pll_cmd,
-	"set pll multiplier and pre divider",
-	PLLSET_CMD_LIST " <mult> <div> <OD>\n"
-);
-
-int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	unsigned int clk;
-	unsigned int freq;
-
-	if (argc != 2)
-		goto getclk_cmd_usage;
-
-	clk = simple_strtoul(argv[1], NULL, 10);
-
-	freq = clk_get_rate(clk);
-	printf("clock index [%d] - frequency %u\n", clk, freq);
-	return 0;
-
-getclk_cmd_usage:
-	return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
-	getclk,	2,	0,	do_getclk_cmd,
-	"get clock rate",
-	"<clk index>\n"
-	"The indexes for clocks:\n"
-	CLOCK_INDEXES_LIST
-);
-
-int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int	psc_module;
-	int	res;
-
-	if (argc != 3)
-		goto psc_cmd_usage;
-
-	psc_module = simple_strtoul(argv[1], NULL, 10);
-	if (strcmp(argv[2], "en") == 0) {
-		res = psc_enable_module(psc_module);
-		printf("psc_enable_module(%d) - %s\n", psc_module,
-		       (res) ? "ERROR" : "OK");
-		return 0;
-	}
-
-	if (strcmp(argv[2], "di") == 0) {
-		res = psc_disable_module(psc_module);
-		printf("psc_disable_module(%d) - %s\n", psc_module,
-		       (res) ? "ERROR" : "OK");
-		return 0;
-	}
-
-	if (strcmp(argv[2], "domain") == 0) {
-		res = psc_disable_domain(psc_module);
-		printf("psc_disable_domain(%d) - %s\n", psc_module,
-		       (res) ? "ERROR" : "OK");
-		return 0;
-	}
-
-psc_cmd_usage:
-	return cmd_usage(cmdtp);
-}
-
-U_BOOT_CMD(
-	psc,	3,	0,	do_psc_cmd,
-	"<enable/disable psc module os disable domain>",
-	"<mod/domain index> <en|di|domain>\n"
-	"Intended to control Power and Sleep Controller (PSC) domains and\n"
-	"modules. The module or domain index exectly corresponds to ones\n"
-	"listed in official TRM. For instance, to enable MSMC RAM clock\n"
-	"domain use command: psc 14 en.\n"
-);
diff --git a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
deleted file mode 100644
index ea78ad8fd5..0000000000
--- a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * Keystone2: DDR3 test commands
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/ddr3.h>
-#include <common.h>
-#include <command.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define DDR_MIN_ADDR		CONFIG_SYS_SDRAM_BASE
-
-#define DDR_REMAP_ADDR		0x80000000
-#define ECC_START_ADDR1		((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17)
-
-#define ECC_END_ADDR1		(((gd->start_addr_sp - DDR_REMAP_ADDR - \
-				 CONFIG_STACKSIZE) >> 17) - 2)
-
-#define DDR_TEST_BURST_SIZE	1024
-
-static int ddr_memory_test(u32 start_address, u32 end_address, int quick)
-{
-	u32 index_start, value, index;
-
-	index_start = start_address;
-
-	while (1) {
-		/* Write a pattern */
-		for (index = index_start;
-				index < index_start + DDR_TEST_BURST_SIZE;
-				index += 4)
-			__raw_writel(index, index);
-
-		/* Read and check the pattern */
-		for (index = index_start;
-				index < index_start + DDR_TEST_BURST_SIZE;
-				index += 4) {
-			value = __raw_readl(index);
-			if (value != index) {
-				printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
-				       index, value, __raw_readl(index));
-
-				return -1;
-			}
-		}
-
-		index_start += DDR_TEST_BURST_SIZE;
-		if (index_start >= end_address)
-			break;
-
-		if (quick)
-			continue;
-
-		/* Write a pattern for complementary values */
-		for (index = index_start;
-		     index < index_start + DDR_TEST_BURST_SIZE;
-		     index += 4)
-			__raw_writel((u32)~index, index);
-
-		/* Read and check the pattern */
-		for (index = index_start;
-		     index < index_start + DDR_TEST_BURST_SIZE;
-		     index += 4) {
-			value = __raw_readl(index);
-			if (value != ~index) {
-				printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
-				       index, value, __raw_readl(index));
-
-				return -1;
-			}
-		}
-
-		index_start += DDR_TEST_BURST_SIZE;
-		if (index_start >= end_address)
-			break;
-
-		/* Write a pattern */
-		for (index = index_start;
-		     index < index_start + DDR_TEST_BURST_SIZE;
-		     index += 2)
-			__raw_writew((u16)index, index);
-
-		/* Read and check the pattern */
-		for (index = index_start;
-		     index < index_start + DDR_TEST_BURST_SIZE;
-		     index += 2) {
-			value = __raw_readw(index);
-			if (value != (u16)index) {
-				printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
-				       index, value, __raw_readw(index));
-
-				return -1;
-			}
-		}
-
-		index_start += DDR_TEST_BURST_SIZE;
-		if (index_start >= end_address)
-			break;
-
-		/* Write a pattern */
-		for (index = index_start;
-		     index < index_start + DDR_TEST_BURST_SIZE;
-		     index += 1)
-			__raw_writeb((u8)index, index);
-
-		/* Read and check the pattern */
-		for (index = index_start;
-		     index < index_start + DDR_TEST_BURST_SIZE;
-		     index += 1) {
-			value = __raw_readb(index);
-			if (value != (u8)index) {
-				printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
-				       index, value, __raw_readb(index));
-
-				return -1;
-			}
-		}
-
-		index_start += DDR_TEST_BURST_SIZE;
-		if (index_start >= end_address)
-			break;
-	}
-
-	puts("ddr memory test PASSED!\n");
-	return 0;
-}
-
-static int ddr_memory_compare(u32 address1, u32 address2, u32 size)
-{
-	u32 index, value, index2, value2;
-
-	for (index = address1, index2 = address2;
-	     index < address1 + size;
-	     index += 4, index2 += 4) {
-		value = __raw_readl(index);
-		value2 = __raw_readl(index2);
-
-		if (value != value2) {
-			printf("ddr_memory_test: Compare failed at address = 0x%x value = 0x%x, address2 = 0x%x value2 = 0x%x\n",
-			       index, value, index2, value2);
-
-			return -1;
-		}
-	}
-
-	puts("ddr memory compare PASSED!\n");
-	return 0;
-}
-
-static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err)
-{
-	u32 value1, value2, value3;
-
-	puts("Disabling DDR ECC ...\n");
-	ddr3_disable_ecc(base);
-
-	value1 = __raw_readl(address);
-	value2 = value1 ^ ecc_err;
-	__raw_writel(value2, address);
-
-	value3 = __raw_readl(address);
-	printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
-	       address, value1, value2, ecc_err, value3);
-
-	__raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16),
-		     base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
-
-	puts("Enabling DDR ECC ...\n");
-	ddr3_enable_ecc(base, 1);
-
-	value1 = __raw_readl(address);
-	printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1);
-
-	ddr3_check_ecc_int(base);
-	return 0;
-}
-
-static int do_ddr_test(cmd_tbl_t *cmdtp,
-		       int flag, int argc, char * const argv[])
-{
-	u32 start_addr, end_addr, size, ecc_err;
-
-	if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
-		if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) {
-			puts("ECC RMW isn't supported for this SOC\n");
-			return 1;
-		}
-
-		start_addr = simple_strtoul(argv[2], NULL, 16);
-		ecc_err = simple_strtoul(argv[3], NULL, 16);
-
-		if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
-		    (start_addr > (CONFIG_SYS_SDRAM_BASE +
-		     CONFIG_MAX_RAM_BANK_SIZE - 1))) {
-			puts("Invalid address!\n");
-			return cmd_usage(cmdtp);
-		}
-
-		ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE,
-				   start_addr, ecc_err);
-		return 0;
-	}
-
-	if (!(((argc == 4) && (strncmp(argv[1], "test", 5) == 0)) ||
-	      ((argc == 5) && (strncmp(argv[1], "compare", 8) == 0))))
-		return cmd_usage(cmdtp);
-
-	start_addr = simple_strtoul(argv[2], NULL, 16);
-	end_addr = simple_strtoul(argv[3], NULL, 16);
-
-	if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
-	    (start_addr > (CONFIG_SYS_SDRAM_BASE +
-	     CONFIG_MAX_RAM_BANK_SIZE - 1)) ||
-	    (end_addr < CONFIG_SYS_SDRAM_BASE) ||
-	    (end_addr > (CONFIG_SYS_SDRAM_BASE +
-	     CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) {
-		puts("Invalid start or end address!\n");
-		return cmd_usage(cmdtp);
-	}
-
-	puts("Please wait ...\n");
-	if (argc == 5) {
-		size = simple_strtoul(argv[4], NULL, 16);
-		ddr_memory_compare(start_addr, end_addr, size);
-	} else {
-		ddr_memory_test(start_addr, end_addr, 0);
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(ddr,	5, 1, do_ddr_test,
-	   "DDR3 test",
-	   "test <start_addr in hex> <end_addr in hex> - test DDR from start\n"
-	   "	address to end address\n"
-	   "ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n"
-	   "	compare DDR data of (size) bytes from start address to end\n"
-	   "	address\n"
-	   "ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n"
-	   "	in DDR data at <addr>, the command will read a 32-bit data\n"
-	   "	from <addr>, and write (data ^ bit_err) back to <addr>\n"
-);
diff --git a/arch/arm/cpu/armv7/keystone/cmd_mon.c b/arch/arm/cpu/armv7/keystone/cmd_mon.c
deleted file mode 100644
index f9f58a37df..0000000000
--- a/arch/arm/cpu/armv7/keystone/cmd_mon.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * K2HK: secure kernel command file
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-asm(".arch_extension sec\n\t");
-
-static int mon_install(u32 addr, u32 dpsc, u32 freq)
-{
-	int result;
-
-	__asm__ __volatile__ (
-		"stmfd r13!, {lr}\n"
-		"mov r0, %1\n"
-		"mov r1, %2\n"
-		"mov r2, %3\n"
-		"blx r0\n"
-		"ldmfd r13!, {lr}\n"
-		: "=&r" (result)
-		: "r" (addr), "r" (dpsc), "r" (freq)
-		: "cc", "r0", "r1", "r2", "memory");
-	return result;
-}
-
-static int do_mon_install(cmd_tbl_t *cmdtp, int flag, int argc,
-			  char * const argv[])
-{
-	u32 addr, dpsc_base = 0x1E80000, freq;
-	int     rcode = 0;
-
-	if (argc < 2)
-		return CMD_RET_USAGE;
-
-	freq = clk_get_rate(sys_clk0_6_clk);
-
-	addr = simple_strtoul(argv[1], NULL, 16);
-
-	rcode = mon_install(addr, dpsc_base, freq);
-	printf("## installed monitor, freq [%d], status %d\n",
-	       freq, rcode);
-
-	return 0;
-}
-
-U_BOOT_CMD(mon_install, 2, 0, do_mon_install,
-	   "Install boot kernel at 'addr'",
-	   ""
-);
-
-static void core_spin(void)
-{
-	while (1)
-		; /* forever */;
-}
-
-int mon_power_on(int core_id, void *ep)
-{
-	int result;
-
-	asm volatile (
-		"stmfd  r13!, {lr}\n"
-		"mov r1, %1\n"
-		"mov r2, %2\n"
-		"mov r0, #0\n"
-		"smc	#0\n"
-		"ldmfd  r13!, {lr}\n"
-		: "=&r" (result)
-		: "r" (core_id), "r" (ep)
-		: "cc", "r0", "r1", "r2", "memory");
-	return  result;
-}
-
-int mon_power_off(int core_id)
-{
-	int result;
-
-	asm volatile (
-		"stmfd  r13!, {lr}\n"
-		"mov r1, %1\n"
-		"mov r0, #1\n"
-		"smc	#1\n"
-		"ldmfd  r13!, {lr}\n"
-		: "=&r" (result)
-		: "r" (core_id)
-		: "cc", "r0", "r1", "memory");
-	return  result;
-}
-
-int do_mon_power(cmd_tbl_t *cmdtp, int flag, int argc,
-			char * const argv[])
-{
-	int     rcode = 0, core_id, on;
-	void (*fn)(void);
-
-	fn = core_spin;
-
-	if (argc < 3)
-		return CMD_RET_USAGE;
-
-	core_id = simple_strtoul(argv[1], NULL, 16);
-	on = simple_strtoul(argv[2], NULL, 16);
-
-	if (on)
-		rcode = mon_power_on(core_id, fn);
-	else
-		rcode = mon_power_off(core_id);
-
-	if (on) {
-		if (!rcode)
-			printf("core %d powered on successfully\n", core_id);
-		else
-			printf("core %d power on failure\n", core_id);
-	} else {
-		printf("core %d powered off successfully\n", core_id);
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(mon_power, 3, 0, do_mon_power,
-	   "Power On/Off secondary core",
-	   "mon_power <coreid> <oper>\n"
-	   "- coreid (1-3) and oper (1 - ON, 0 - OFF)\n"
-	   ""
-);
diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c
deleted file mode 100644
index 923906afb5..0000000000
--- a/arch/arm/cpu/armv7/keystone/ddr3.c
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
- * Keystone2: DDR3 initialization
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <asm/io.h>
-#include <common.h>
-#include <asm/arch/msmc.h>
-#include <asm/arch/ddr3.h>
-#include <asm/arch/psc_defs.h>
-
-#include <asm/ti-common/ti-edma3.h>
-
-#define DDR3_EDMA_BLK_SIZE_SHIFT	10
-#define DDR3_EDMA_BLK_SIZE		(1 << DDR3_EDMA_BLK_SIZE_SHIFT)
-#define DDR3_EDMA_BCNT			0x8000
-#define DDR3_EDMA_CCNT			1
-#define DDR3_EDMA_XF_SIZE		(DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
-#define DDR3_EDMA_SLOT_NUM		1
-
-void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
-{
-	unsigned int tmp;
-
-	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET)
-		 & 0x00000001) != 0x00000001)
-		;
-
-	__raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET);
-
-	tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET);
-	tmp &= ~(phy_cfg->pgcr1_mask);
-	tmp |= phy_cfg->pgcr1_val;
-	__raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET);
-
-	__raw_writel(phy_cfg->ptr0,   base + KS2_DDRPHY_PTR0_OFFSET);
-	__raw_writel(phy_cfg->ptr1,   base + KS2_DDRPHY_PTR1_OFFSET);
-	__raw_writel(phy_cfg->ptr3,  base + KS2_DDRPHY_PTR3_OFFSET);
-	__raw_writel(phy_cfg->ptr4,  base + KS2_DDRPHY_PTR4_OFFSET);
-
-	tmp =  __raw_readl(base + KS2_DDRPHY_DCR_OFFSET);
-	tmp &= ~(phy_cfg->dcr_mask);
-	tmp |= phy_cfg->dcr_val;
-	__raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET);
-
-	__raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET);
-	__raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET);
-	__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
-	__raw_writel(phy_cfg->mr0,   base + KS2_DDRPHY_MR0_OFFSET);
-	__raw_writel(phy_cfg->mr1,   base + KS2_DDRPHY_MR1_OFFSET);
-	__raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
-	__raw_writel(phy_cfg->dtcr,  base + KS2_DDRPHY_DTCR_OFFSET);
-	__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
-
-	__raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET);
-	__raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET);
-	__raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET);
-
-	__raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET);
-	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
-		;
-
-	__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
-	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
-		;
-}
-
-void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
-{
-	__raw_writel(emif_cfg->sdcfg,  base + KS2_DDR3_SDCFG_OFFSET);
-	__raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET);
-	__raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET);
-	__raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET);
-	__raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET);
-	__raw_writel(emif_cfg->zqcfg,  base + KS2_DDR3_ZQCFG_OFFSET);
-	__raw_writel(emif_cfg->sdrfc,  base + KS2_DDR3_SDRFC_OFFSET);
-}
-
-int ddr3_ecc_support_rmw(u32 base)
-{
-	u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);
-
-	/* Check the DDR3 controller ID reg if the controllers
-	   supports ECC RMW or not */
-	if (value == 0x40461C02)
-		return 1;
-
-	return 0;
-}
-
-static void ddr3_ecc_config(u32 base, u32 value)
-{
-	u32 data;
-
-	__raw_writel(value,  base + KS2_DDR3_ECC_CTRL_OFFSET);
-	udelay(100000); /* delay required to synchronize across clock domains */
-
-	if (value & KS2_DDR3_ECC_EN) {
-		/* Clear the 1-bit error count */
-		data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
-		__raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
-
-		/* enable the ECC interrupt */
-		__raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
-			     KS2_DDR3_WR_ECC_ERR_SYS,
-			     base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);
-
-		/* Clear the ECC error interrupt status */
-		__raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
-			     KS2_DDR3_WR_ECC_ERR_SYS,
-			     base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
-	}
-}
-
-static void ddr3_reset_data(u32 base, u32 ddr3_size)
-{
-	u32 mpax[2];
-	u32 seg_num;
-	u32 seg, blks, dst, edma_blks;
-	struct edma3_slot_config slot;
-	struct edma3_channel_config edma_channel;
-	u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };
-
-	/* Setup an edma to copy the 1k block to the entire DDR */
-	puts("\nClear entire DDR3 memory to enable ECC\n");
-
-	/* save the SES MPAX regs */
-	msmc_get_ses_mpax(8, 0, mpax);
-
-	/* setup edma slot 1 configuration */
-	slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
-		   EDMA3_SLOPT_COMP_CODE(0) |
-		   EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
-	slot.bcnt = DDR3_EDMA_BCNT;
-	slot.acnt = DDR3_EDMA_BLK_SIZE;
-	slot.ccnt = DDR3_EDMA_CCNT;
-	slot.src_bidx = 0;
-	slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
-	slot.src_cidx = 0;
-	slot.dst_cidx = 0;
-	slot.link = EDMA3_PARSET_NULL_LINK;
-	slot.bcntrld = 0;
-	edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot);
-
-	/* configure quik edma channel */
-	edma_channel.slot = DDR3_EDMA_SLOT_NUM;
-	edma_channel.chnum = 0;
-	edma_channel.complete_code = 0;
-	/* event trigger after dst update */
-	edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
-	qedma3_start(KS2_EDMA0_BASE, &edma_channel);
-
-	/* DDR3 size in segments (4KB seg size) */
-	seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT);
-
-	for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
-		/* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
-		   access slave interface so that edma driver can access */
-		msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT,
-				     KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G);
-
-		if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
-			edma_blks = KS2_MSMC_MAP_SEG_NUM <<
-					(KS2_MSMC_SEG_SIZE_SHIFT
-					- DDR3_EDMA_BLK_SIZE_SHIFT);
-		else
-			edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT
-					- DDR3_EDMA_BLK_SIZE_SHIFT);
-
-		/* Use edma driver to scrub 2GB DDR memory */
-		for (dst = base, blks = 0; blks < edma_blks;
-		     blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) {
-			edma3_set_src_addr(KS2_EDMA0_BASE,
-					   edma_channel.slot, (u32)edma_src);
-			edma3_set_dest_addr(KS2_EDMA0_BASE,
-					    edma_channel.slot, (u32)dst);
-
-			while (edma3_check_for_transfer(KS2_EDMA0_BASE,
-							&edma_channel))
-				udelay(10);
-		}
-	}
-
-	qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
-
-	/* restore the SES MPAX regs */
-	msmc_set_ses_mpax(8, 0, mpax);
-}
-
-static void ddr3_ecc_init_range(u32 base)
-{
-	u32 ecc_val = KS2_DDR3_ECC_EN;
-	u32 rmw = ddr3_ecc_support_rmw(base);
-
-	if (rmw)
-		ecc_val |= KS2_DDR3_ECC_RMW_EN;
-
-	__raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
-
-	ddr3_ecc_config(base, ecc_val);
-}
-
-void ddr3_enable_ecc(u32 base, int test)
-{
-	u32 ecc_val = KS2_DDR3_ECC_ENABLE;
-	u32 rmw = ddr3_ecc_support_rmw(base);
-
-	if (test)
-		ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN;
-
-	if (!rmw) {
-		if (!test)
-			/* by default, disable ecc when rmw = 0 and no
-			   ecc test */
-			ecc_val = 0;
-	} else {
-		ecc_val |= KS2_DDR3_ECC_RMW_EN;
-	}
-
-	ddr3_ecc_config(base, ecc_val);
-}
-
-void ddr3_disable_ecc(u32 base)
-{
-	ddr3_ecc_config(base, 0);
-}
-
-#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
-static void cic_init(u32 base)
-{
-	/* Disable CIC global interrupts */
-	__raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE);
-
-	/* Set to normal mode, no nesting, no priority hold */
-	__raw_writel(0, base + KS2_CIC_CTRL);
-	__raw_writel(0, base + KS2_CIC_HOST_CTRL);
-
-	/* Enable CIC global interrupts */
-	__raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE);
-}
-
-static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num)
-{
-	/* Map the system interrupt to a CIC channel */
-	__raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num);
-
-	/* Enable CIC system interrupt */
-	__raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET);
-
-	/* Enable CIC Host interrupt */
-	__raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET);
-}
-
-static void ddr3_map_ecc_cic2_irq(u32 base)
-{
-	cic_init(base);
-	cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM,
-			   KS2_CIC2_DDR3_ECC_IRQ_NUM);
-}
-#endif
-
-void ddr3_init_ecc(u32 base)
-{
-	u32 ddr3_size;
-
-	if (!ddr3_ecc_support_rmw(base)) {
-		ddr3_disable_ecc(base);
-		return;
-	}
-
-	ddr3_ecc_init_range(base);
-	ddr3_size = ddr3_get_size();
-	ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
-
-	/* mapping DDR3 ECC system interrupt from CIC2 to GIC */
-#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
-	ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE);
-#endif
-	ddr3_enable_ecc(base, 0);
-}
-
-void ddr3_check_ecc_int(u32 base)
-{
-	char *env;
-	int ecc_test = 0;
-	u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
-
-	env = getenv("ecc_test");
-	if (env)
-		ecc_test = simple_strtol(env, NULL, 0);
-
-	if (value & KS2_DDR3_WR_ECC_ERR_SYS)
-		puts("DDR3 ECC write error interrupted\n");
-
-	if (value & KS2_DDR3_2B_ECC_ERR_SYS) {
-		puts("DDR3 ECC 2-bit error interrupted\n");
-
-		if (!ecc_test) {
-			puts("Reseting the device ...\n");
-			reset_cpu(0);
-		}
-	}
-
-	value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
-	if (value) {
-		printf("1-bit ECC err count: 0x%x\n", value);
-		value = __raw_readl(base +
-				    KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET);
-		printf("1-bit ECC err address log: 0x%x\n", value);
-	}
-}
-
-void ddr3_reset_ddrphy(void)
-{
-	u32 tmp;
-
-	/* Assert DDR3A  PHY reset */
-	tmp = readl(KS2_DDR3APLLCTL1);
-	tmp |= KS2_DDR3_PLLCTRL_PHY_RESET;
-	writel(tmp, KS2_DDR3APLLCTL1);
-
-	/* wait 10us to catch the reset */
-	udelay(10);
-
-	/* Release DDR3A PHY reset */
-	tmp = readl(KS2_DDR3APLLCTL1);
-	tmp &= ~KS2_DDR3_PLLCTRL_PHY_RESET;
-	__raw_writel(tmp, KS2_DDR3APLLCTL1);
-}
-
-#ifdef CONFIG_SOC_K2HK
-/**
- * ddr3_reset_workaround - reset workaround in case if leveling error
- * detected for PG 1.0 and 1.1 k2hk SoCs
- */
-void ddr3_err_reset_workaround(void)
-{
-	unsigned int tmp;
-	unsigned int tmp_a;
-	unsigned int tmp_b;
-
-	/*
-	 * Check for PGSR0 error bits of DDR3 PHY.
-	 * Check for WLERR, QSGERR, WLAERR,
-	 * RDERR, WDERR, REERR, WEERR error to see if they are set or not
-	 */
-	tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
-	tmp_b = __raw_readl(KS2_DDR3B_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET);
-
-	if (((tmp_a & 0x0FE00000) != 0) || ((tmp_b & 0x0FE00000) != 0)) {
-		printf("DDR Leveling Error Detected!\n");
-		printf("DDR3A PGSR0 = 0x%x\n", tmp_a);
-		printf("DDR3B PGSR0 = 0x%x\n", tmp_b);
-
-		/*
-		 * Write Keys to KICK registers to enable writes to registers
-		 * in boot config space
-		 */
-		__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
-		__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
-
-		/*
-		 * Move DDR3A Module out of reset isolation by setting
-		 * MDCTL23[12] = 0
-		 */
-		tmp_a = __raw_readl(KS2_PSC_BASE +
-				    PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
-
-		tmp_a = PSC_REG_MDCTL_SET_RESET_ISO(tmp_a, 0);
-		__raw_writel(tmp_a, KS2_PSC_BASE +
-			     PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3A));
-
-		/*
-		 * Move DDR3B Module out of reset isolation by setting
-		 * MDCTL24[12] = 0
-		 */
-		tmp_b = __raw_readl(KS2_PSC_BASE +
-				    PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
-		tmp_b = PSC_REG_MDCTL_SET_RESET_ISO(tmp_b, 0);
-		__raw_writel(tmp_b, KS2_PSC_BASE +
-			     PSC_REG_MDCTL(KS2_LPSC_EMIF4F_DDR3B));
-
-		/*
-		 * Write 0x5A69 Key to RSTCTRL[15:0] to unlock writes
-		 * to RSTCTRL and RSTCFG
-		 */
-		tmp = __raw_readl(KS2_RSTCTRL);
-		tmp &= KS2_RSTCTRL_MASK;
-		tmp |= KS2_RSTCTRL_KEY;
-		__raw_writel(tmp, KS2_RSTCTRL);
-
-		/*
-		 * Set PLL Controller to drive hard reset on SW trigger by
-		 * setting RSTCFG[13] = 0
-		 */
-		tmp = __raw_readl(KS2_RSTCTRL_RSCFG);
-		tmp &= ~KS2_RSTYPE_PLL_SOFT;
-		__raw_writel(tmp, KS2_RSTCTRL_RSCFG);
-
-		reset_cpu(0);
-	}
-}
-#endif
diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c
deleted file mode 100644
index c96845c4e2..0000000000
--- a/arch/arm/cpu/armv7/keystone/init.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Keystone2: Architecture initialization
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <asm/arch/msmc.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/psc_defs.h>
-
-#define MAX_PCI_PORTS		2
-enum pci_mode	{
-	ENDPOINT,
-	LEGACY_ENDPOINT,
-	ROOTCOMPLEX,
-};
-
-#define DEVCFG_MODE_MASK		(BIT(2) | BIT(1))
-#define DEVCFG_MODE_SHIFT		1
-
-void chip_configuration_unlock(void)
-{
-	__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
-	__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
-}
-
-#ifdef CONFIG_SOC_K2L
-void osr_init(void)
-{
-	u32 i;
-	u32 j;
-	u32 val;
-	u32 base = KS2_OSR_CFG_BASE;
-	u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
-
-	/* Enable the OSR clock domain */
-	psc_enable_module(KS2_LPSC_OSR);
-
-	/* Disable OSR ECC check for all the ram banks */
-	for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
-		val = i | KS2_OSR_ECC_VEC_TRIG_RD |
-			(KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
-
-		writel(val , base + KS2_OSR_ECC_VEC);
-
-		/**
-		 * wait till read is done.
-		 * Print should be added after earlyprintk support is added.
-		 */
-		for (j = 0; j < 10000; j++) {
-			val = readl(base + KS2_OSR_ECC_VEC);
-			if (val & KS2_OSR_ECC_VEC_RD_DONE)
-				break;
-		}
-
-		ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
-						KS2_OSR_ECC_CTRL_CHK;
-
-		writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
-		writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
-	}
-
-	/* Reset OSR memory to all zeros */
-	for (i = 0; i < KS2_OSR_SIZE; i += 4)
-		writel(0, KS2_OSR_DATA_BASE + i);
-
-	/* Enable OSR ECC check for all the ram banks */
-	for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
-		writel(ecc_ctrl[i] |
-		       KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
-}
-#endif
-
-/* Function to set up PCIe mode */
-static void config_pcie_mode(int pcie_port,  enum pci_mode mode)
-{
-	u32 val = __raw_readl(KS2_DEVCFG);
-
-	if (pcie_port >= MAX_PCI_PORTS)
-		return;
-
-	/**
-	 * each pci port has two bits for mode and it starts at
-	 * bit 1. So use port number to get the right bit position.
-	 */
-	pcie_port <<= 1;
-	val &= ~(DEVCFG_MODE_MASK << pcie_port);
-	val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
-	__raw_writel(val, KS2_DEVCFG);
-}
-
-int arch_cpu_init(void)
-{
-	chip_configuration_unlock();
-	icache_enable();
-
-	msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
-	msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
-	msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
-	msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
-
-	/* Initialize the PCIe-0 to work as Root Complex */
-	config_pcie_mode(0, ROOTCOMPLEX);
-#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
-	msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
-	/* Initialize the PCIe-1 to work as Root Complex */
-	config_pcie_mode(1, ROOTCOMPLEX);
-#endif
-#ifdef CONFIG_SOC_K2L
-	osr_init();
-#endif
-
-	/*
-	 * just initialise the COM2 port so that TI specific
-	 * UART register PWREMU_MGMT is initialized. Linux UART
-	 * driver doesn't handle this.
-	 */
-	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
-		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
-
-	return 0;
-}
-
-void reset_cpu(ulong addr)
-{
-	volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
-	u32 tmp;
-
-	tmp = *rstctrl & KS2_RSTCTRL_MASK;
-	*rstctrl = tmp | KS2_RSTCTRL_KEY;
-
-	*rstctrl &= KS2_RSTCTRL_SWRST;
-
-	for (;;)
-		;
-}
-
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_DCACHE_OFF
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-#endif
-}
diff --git a/arch/arm/cpu/armv7/keystone/keystone.c b/arch/arm/cpu/armv7/keystone/keystone.c
deleted file mode 100644
index 11a9357db4..0000000000
--- a/arch/arm/cpu/armv7/keystone/keystone.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Keystone EVM : Board initialization
- *
- * (C) Copyright 2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mon.h>
-#include <asm/arch/psc_defs.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/hardware.h>
-
-/**
- * cpu_to_bus - swap bytes of the 32-bit data if the device is BE
- * @ptr - array of data
- * @length - lenght of data array
- */
-int cpu_to_bus(u32 *ptr, u32 length)
-{
-	u32 i;
-
-	if (!(readl(KS2_DEVSTAT) & 0x1))
-		for (i = 0; i < length; i++, ptr++)
-			*ptr = cpu_to_be32(*ptr);
-
-	return 0;
-}
-
-static int turn_off_myself(void)
-{
-	printf("Turning off ourselves\r\n");
-	mon_power_off(0);
-
-	psc_disable_module(KS2_LPSC_TETRIS);
-	psc_disable_domain(KS2_TETRIS_PWR_DOMAIN);
-
-	asm volatile ("isb\n"
-		      "dsb\n"
-		      "wfi\n");
-
-	printf("What! Should not see that\n");
-	return 0;
-}
-
-static void turn_off_all_dsps(int num_dsps)
-{
-	int i;
-
-	for (i = 0; i < num_dsps; i++) {
-		if (psc_disable_module(i + KS2_LPSC_GEM_0))
-			printf("Cannot disable module for #%d DSP", i);
-
-		if (psc_disable_domain(i + 8))
-			printf("Cannot disable domain for #%d DSP", i);
-	}
-}
-
-int do_killme_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	return turn_off_myself();
-}
-
-U_BOOT_CMD(
-	killme, 1,      0,      do_killme_cmd,
-	"turn off main ARM core",
-	"turn off main ARM core. Should not live after that :(\n"
-);
-
-int misc_init_r(void)
-{
-	char *env;
-	long ks2_debug = 0;
-
-	env = getenv("ks2_debug");
-
-	if (env)
-		ks2_debug = simple_strtol(env, NULL, 0);
-
-	if ((ks2_debug & DBG_LEAVE_DSPS_ON) == 0)
-		turn_off_all_dsps(KS2_NUM_DSPS);
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c
deleted file mode 100644
index 7899141d54..0000000000
--- a/arch/arm/cpu/armv7/keystone/msmc.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * MSMC controller utilities
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/msmc.h>
-
-struct mpax {
-	u32	mpaxl;
-	u32	mpaxh;
-};
-
-struct msms_regs {
-	u32	pid;
-	u32	_res_04;
-	u32	smcerrar;
-	u32	smcerrxr;
-	u32	smedcc;
-	u32	smcea;
-	u32	smsecc;
-	u32	smpfar;
-	u32	smpfxr;
-	u32	smpfr;
-	u32	smpfcr;
-	u32	_res_2c;
-	u32	sbndc[8];
-	u32	sbndm;
-	u32	sbnde;
-	u32	_res_58;
-	u32	cfglck;
-	u32	cfgulck;
-	u32	cfglckstat;
-	u32	sms_mpax_lck;
-	u32	sms_mpax_ulck;
-	u32	sms_mpax_lckstat;
-	u32	ses_mpax_lck;
-	u32	ses_mpax_ulck;
-	u32	ses_mpax_lckstat;
-	u32	smestat;
-	u32	smirstat;
-	u32	smirc;
-	u32	smiestat;
-	u32	smiec;
-	u32	_res_94_c0[12];
-	u32	smncerrar;
-	u32	smncerrxr;
-	u32	smncea;
-	u32	_res_d0_1fc[76];
-	struct mpax sms[16][8];
-	struct mpax ses[16][8];
-};
-
-
-void msmc_share_all_segments(int priv_id)
-{
-	struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
-	int j;
-
-	for (j = 0; j < 8; j++) {
-		msmc->sms[priv_id][j].mpaxh &= 0xffffff7ful;
-		msmc->ses[priv_id][j].mpaxh &= 0xffffff7ful;
-	}
-}
-
-void msmc_map_ses_segment(int priv_id, int ses_pair,
-			  u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size)
-{
-	struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
-
-	msmc->ses[priv_id][ses_pair].mpaxh = src_pfn << 12 |
-					     (size & 0x1f) | 0x80;
-	msmc->ses[priv_id][ses_pair].mpaxl = dst_pfn << 8 | 0x3f;
-}
-
-void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
-{
-	struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
-
-	*mpax++ = msmc->ses[priv_id][ses_pair].mpaxl;
-	*mpax = msmc->ses[priv_id][ses_pair].mpaxh;
-}
-
-void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
-{
-	struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
-
-	msmc->ses[priv_id][ses_pair].mpaxl = *mpax++;
-	msmc->ses[priv_id][ses_pair].mpaxh = *mpax;
-}
diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/cpu/armv7/keystone/psc.c
deleted file mode 100644
index 237e776e87..0000000000
--- a/arch/arm/cpu/armv7/keystone/psc.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * Keystone: PSC configuration module
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <asm-generic/errno.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/arch/psc_defs.h>
-
-int psc_delay(void)
-{
-	udelay(10);
-	return 10;
-}
-
-/*
- * FUNCTION PURPOSE: Wait for end of transitional state
- *
- * DESCRIPTION: Polls pstat for the selected domain and waits for transitions
- *              to be complete.
- *
- *              Since this is boot loader code it is *ASSUMED* that interrupts
- *              are disabled and no other core is mucking around with the psc
- *              at the same time.
- *
- *              Returns 0 when the domain is free. Returns -1 if a timeout
- *              occurred waiting for the completion.
- */
-int psc_wait(u32 domain_num)
-{
-	u32 retry;
-	u32 ptstat;
-
-	/*
-	 * Do nothing if the power domain is in transition. This should never
-	 * happen since the boot code is the only software accesses psc.
-	 * It's still remotely possible that the hardware state machines
-	 * initiate transitions.
-	 * Don't trap if the domain (or a module in this domain) is
-	 * stuck in transition.
-	 */
-	retry = 0;
-
-	do {
-		ptstat = __raw_readl(KS2_PSC_BASE + PSC_REG_PSTAT);
-		ptstat = ptstat & (1 << domain_num);
-	} while ((ptstat != 0) && ((retry += psc_delay()) <
-		 PSC_PTSTAT_TIMEOUT_LIMIT));
-
-	if (retry >= PSC_PTSTAT_TIMEOUT_LIMIT)
-		return -1;
-
-	return 0;
-}
-
-u32 psc_get_domain_num(u32 mod_num)
-{
-	u32 domain_num;
-
-	/* Get the power domain associated with the module number */
-	domain_num = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
-	domain_num = PSC_REG_MDCFG_GET_PD(domain_num);
-
-	return domain_num;
-}
-
-/*
- * FUNCTION PURPOSE: Power up/down a module
- *
- * DESCRIPTION: Powers up/down the requested module and the associated power
- *		domain if required. No action is taken it the module is
- *		already powered up/down.
- *
- *              This only controls modules. The domain in which the module
- *              resides will be left in the power on state. Multiple modules
- *              can exist in a power domain, so powering down the domain based
- *              on a single module is not done.
- *
- *              Returns 0 on success, -1 if the module can't be powered up, or
- *              if there is a timeout waiting for the transition.
- */
-int psc_set_state(u32 mod_num, u32 state)
-{
-	u32 domain_num;
-	u32 pdctl;
-	u32 mdctl;
-	u32 ptcmd;
-	u32 reset_iso;
-	u32 v;
-
-	/*
-	 * Get the power domain associated with the module number, and reset
-	 * isolation functionality
-	 */
-	v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
-	domain_num = PSC_REG_MDCFG_GET_PD(v);
-	reset_iso  = PSC_REG_MDCFG_GET_RESET_ISO(v);
-
-	/* Wait for the status of the domain/module to be non-transitional */
-	if (psc_wait(domain_num) != 0)
-		return -1;
-
-	/*
-	 * Perform configuration even if the current status matches the
-	 * existing state
-	 *
-	 * Set the next state of the power domain to on. It's OK if the domain
-	 * is always on. This code will not ever power down a domain, so no
-	 * change is made if the new state is power down.
-	 */
-	if (state == PSC_REG_VAL_MDCTL_NEXT_ON) {
-		pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
-		pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl,
-					       PSC_REG_VAL_PDCTL_NEXT_ON);
-		__raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
-	}
-
-	/* Set the next state for the module to enabled/disabled */
-	mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
-	mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state);
-	mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso);
-	__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
-
-	/* Trigger the enable */
-	ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
-	ptcmd |= (u32)(1<<domain_num);
-	__raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);
-
-	/* Wait on the complete */
-	return psc_wait(domain_num);
-}
-
-/*
- * FUNCTION PURPOSE: Power up a module
- *
- * DESCRIPTION: Powers up the requested module and the associated power domain
- *              if required. No action is taken it the module is already
- *              powered up.
- *
- *              Returns 0 on success, -1 if the module can't be powered up, or
- *              if there is a timeout waiting for the transition.
- */
-int psc_enable_module(u32 mod_num)
-{
-	u32 mdctl;
-
-	/* Set the bit to apply reset */
-	mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
-	if ((mdctl & 0x3f) == PSC_REG_VAL_MDSTAT_STATE_ON)
-		return 0;
-
-	return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_ON);
-}
-
-/*
- * FUNCTION PURPOSE: Power down a module
- *
- * DESCRIPTION: Powers down the requested module.
- *
- *              Returns 0 on success, -1 on failure or timeout.
- */
-int psc_disable_module(u32 mod_num)
-{
-	u32 mdctl;
-
-	/* Set the bit to apply reset */
-	mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
-	if ((mdctl & 0x3f) == 0)
-		return 0;
-	mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0);
-	__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
-
-	return psc_set_state(mod_num, PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE);
-}
-
-/*
- * FUNCTION PURPOSE: Set the reset isolation bit in mdctl
- *
- * DESCRIPTION: The reset isolation enable bit is set. The state of the module
- *              is not changed. Returns 0 if the module config showed that
- *              reset isolation is supported. Returns 1 otherwise. This is not
- *              an error, but setting the bit in mdctl has no effect.
- */
-int psc_set_reset_iso(u32 mod_num)
-{
-	u32 v;
-	u32 mdctl;
-
-	/* Set the reset isolation bit */
-	mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
-	mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1);
-	__raw_writel(mdctl, KS2_PSC_BASE + PSC_REG_MDCTL(mod_num));
-
-	v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num));
-	if (PSC_REG_MDCFG_GET_RESET_ISO(v) == 1)
-		return 0;
-
-	return 1;
-}
-
-/*
- * FUNCTION PURPOSE: Disable a power domain
- *
- * DESCRIPTION: The power domain is disabled
- */
-int psc_disable_domain(u32 domain_num)
-{
-	u32 pdctl;
-	u32 ptcmd;
-
-	pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
-	pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, PSC_REG_VAL_PDCTL_NEXT_OFF);
-	pdctl = PSC_REG_PDCTL_SET_PDMODE(pdctl, PSC_REG_VAL_PDCTL_PDMODE_SLEEP);
-	__raw_writel(pdctl, KS2_PSC_BASE + PSC_REG_PDCTL(domain_num));
-
-	ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD);
-	ptcmd |= (u32)(1 << domain_num);
-	__raw_writel(ptcmd, KS2_PSC_BASE + PSC_REG_PTCMD);
-
-	return psc_wait(domain_num);
-}
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index ce2d92f5a6..1a640bbb9c 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -8,14 +8,214 @@
 #include <asm/arch/clock.h>
 #include <asm/io.h>
 #include <asm/arch/immap_ls102xa.h>
+#include <asm/cache.h>
+#include <asm/system.h>
 #include <tsec.h>
 #include <netdev.h>
 #include <fsl_esdhc.h>
 
 #include "fsl_epu.h"
 
+#define DCSR_RCPM2_BLOCK_OFFSET	0x223000
+#define DCSR_RCPM2_CPMFSMCR0	0x400
+#define DCSR_RCPM2_CPMFSMSR0	0x404
+#define DCSR_RCPM2_CPMFSMCR1	0x414
+#define DCSR_RCPM2_CPMFSMSR1	0x418
+#define CPMFSMSR_FSM_STATE_MASK	0x7f
+
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+/*
+ * Bit[1] of the descriptor indicates the descriptor type,
+ * and bit[0] indicates whether the descriptor is valid.
+ */
+#define PMD_TYPE_TABLE		0x3
+#define PMD_TYPE_SECT		0x1
+
+/* AttrIndx[2:0] */
+#define PMD_ATTRINDX(t)		((t) << 2)
+
+/* Section */
+#define PMD_SECT_AF		(1 << 10)
+
+#define BLOCK_SIZE_L1		(1UL << 30)
+#define BLOCK_SIZE_L2		(1UL << 21)
+
+/* TTBCR flags */
+#define TTBCR_EAE		(1 << 31)
+#define TTBCR_T0SZ(x)		((x) << 0)
+#define TTBCR_T1SZ(x)		((x) << 16)
+#define TTBCR_USING_TTBR0	(TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
+#define TTBCR_IRGN0_NC		(0 << 8)
+#define TTBCR_IRGN0_WBWA	(1 << 8)
+#define TTBCR_IRGN0_WT		(2 << 8)
+#define TTBCR_IRGN0_WBNWA	(3 << 8)
+#define TTBCR_IRGN0_MASK	(3 << 8)
+#define TTBCR_ORGN0_NC		(0 << 10)
+#define TTBCR_ORGN0_WBWA	(1 << 10)
+#define TTBCR_ORGN0_WT		(2 << 10)
+#define TTBCR_ORGN0_WBNWA	(3 << 10)
+#define TTBCR_ORGN0_MASK	(3 << 10)
+#define TTBCR_SHARED_NON	(0 << 12)
+#define TTBCR_SHARED_OUTER	(2 << 12)
+#define TTBCR_SHARED_INNER	(3 << 12)
+#define TTBCR_EPD0		(0 << 7)
+#define TTBCR			(TTBCR_SHARED_NON | \
+				 TTBCR_ORGN0_NC	| \
+				 TTBCR_IRGN0_NC	| \
+				 TTBCR_USING_TTBR0 | \
+				 TTBCR_EAE)
+
+/*
+ * Memory region attributes for LPAE (defined in pgtable):
+ *
+ * n = AttrIndx[2:0]
+ *
+ *		              n       MAIR
+ *	UNCACHED              000     00000000
+ *	BUFFERABLE            001     01000100
+ *	DEV_WC                001     01000100
+ *	WRITETHROUGH          010     10101010
+ *	WRITEBACK             011     11101110
+ *	DEV_CACHED            011     11101110
+ *	DEV_SHARED            100     00000100
+ *	DEV_NONSHARED         100     00000100
+ *	unused                101
+ *	unused                110
+ *	WRITEALLOC            111     11111111
+ */
+#define MT_MAIR0		0xeeaa4400
+#define MT_MAIR1		0xff000004
+#define MT_STRONLY_ORDER	0
+#define MT_NORMAL_NC		1
+#define MT_DEVICE_MEM		4
+#define MT_NORMAL		7
+
+/* The phy_addr must be aligned to 4KB */
+static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr)
+{
+	u32 value = phy_addr | PMD_TYPE_TABLE;
+
+	page_table[2 * index] = value;
+	page_table[2 * index + 1] = 0;
+}
+
+/* The phy_addr must be aligned to 4KB */
+static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr,
+				 u32 memory_type)
+{
+	u64 value;
+
+	value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF;
+	value |= PMD_ATTRINDX(memory_type);
+	page_table[2 * index] = value & 0xFFFFFFFF;
+	page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF;
+}
+
+/*
+ * Start MMU after DDR is available, we create MMU table in DRAM.
+ * The base address of TTLB is gd->arch.tlb_addr. We use two
+ * levels of translation tables here to cover 40-bit address space.
+ *
+ * The TTLBs are located at PHY 2G~4G.
+ *
+ * VA mapping:
+ *
+ *  -------  <---- 0GB
+ * |       |
+ * |       |
+ * |-------| <---- 0x24000000
+ * |///////|  ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
+ * |-------| <---- 0x300000000
+ * |       |
+ * |-------| <---- 0x34000000
+ * |///////|  ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
+ * |-------| <---- 0x40000000
+ * |       |
+ * |-------| <---- 0x80000000 DDR0 space start
+ * |\\\\\\\|
+ *.|\\\\\\\|  ===> 2GB VA map for 2GB DDR0 Memory space
+ * |\\\\\\\|
+ *  -------  <---- 4GB DDR0 space end
+ */
+static void mmu_setup(void)
+{
+	u32 *level0_table = (u32 *)gd->arch.tlb_addr;
+	u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);
+	u64 va_start = 0;
+	u32 reg;
+	int i;
+
+	/* Level 0 Table 2-3 are used to map DDR */
+	set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL);
+	set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL);
+	/* Level 0 Table 1 is used to map device */
+	set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM);
+	/* Level 0 Table 0 is used to map device including PCIe MEM */
+	set_pgtable(level0_table, 0, (u32)level1_table);
+
+	/* Level 1 has 512 entries */
+	for (i = 0; i < 512; i++) {
+		/* Mapping for PCIe 1 */
+		if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
+		    va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
+				 CONFIG_SYS_PCIE_MMAP_SIZE))
+			set_pgsection(level1_table, i,
+				      CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
+				      MT_DEVICE_MEM);
+		/* Mapping for PCIe 2 */
+		else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
+			 va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
+				     CONFIG_SYS_PCIE_MMAP_SIZE))
+			set_pgsection(level1_table, i,
+				      CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
+				      MT_DEVICE_MEM);
+		else
+			set_pgsection(level1_table, i,
+				      va_start,
+				      MT_DEVICE_MEM);
+		va_start += BLOCK_SIZE_L2;
+	}
+
+	asm volatile("dsb sy;isb");
+	asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */
+			: : "r" (TTBCR) : "memory");
+	asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */
+			: : "r" ((u32)level0_table), "r" (0) : "memory");
+	asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */
+			: : "r" (MT_MAIR0) : "memory");
+	asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */
+			: : "r" (MT_MAIR1) : "memory");
+
+	/* Set the access control to all-supervisor */
+	asm volatile("mcr p15, 0, %0, c3, c0, 0"
+		     : : "r" (~0));
+
+	/* Enable the mmu */
+	reg = get_cr();
+	set_cr(reg | CR_M);
+}
+
+/*
+ * This function is called from lib/board.c. It recreates MMU
+ * table in main memory. MMU and i/d-cache are enabled here.
+ */
+void enable_caches(void)
+{
+	/* Invalidate all TLB */
+	mmu_page_table_flush(gd->arch.tlb_addr,
+			     gd->arch.tlb_addr +  gd->arch.tlb_size);
+	/* Set up and enable mmu */
+	mmu_setup();
+
+	/* Invalidate & Enable d-cache */
+	invalidate_dcache_all();
+	set_cr(get_cr() | CR_C);
+}
+#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
@@ -78,16 +278,6 @@ int print_cpuinfo(void)
 }
 #endif
 
-void enable_caches(void)
-{
-#ifndef CONFIG_SYS_ICACHE_OFF
-	icache_enable();
-#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
-	dcache_enable();
-#endif
-}
-
 #ifdef CONFIG_FSL_ESDHC
 int cpu_mmc_init(bd_t *bis)
 {
@@ -107,6 +297,27 @@ int cpu_eth_init(bd_t *bis)
 int arch_cpu_init(void)
 {
 	void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+	void *rcpm2_base =
+		(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+	u32 state;
+
+	/*
+	 * The RCPM FSM state may not be reset after power-on.
+	 * So, reset them.
+	 */
+	state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
+		CPMFSMSR_FSM_STATE_MASK;
+	if (state != 0) {
+		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
+		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
+	}
+
+	state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
+		CPMFSMSR_FSM_STATE_MASK;
+	if (state != 0) {
+		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
+		out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
+	}
 
 	/*
 	 * After wakeup from deep sleep, Clear EPU registers
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index e601ba1886..c01a98f719 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -252,6 +252,8 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
+	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
+	writel(regs->sdram_config_init, &emif->emif_sdram_config);
 	/*
 	 * Set SDRAM_CONFIG and PHY control registers to locked frequency
 	 * and RL =7. As the default values of the Mode Registers are not
@@ -265,7 +267,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
 	writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
 	writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
 
-	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 
 	/*
@@ -274,6 +275,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
 	 */
 	if (is_dra7xx()) {
 		do_ext_phy_settings(base, regs);
+		writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
 		writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 		writel(regs->sdram_config_init, &emif->emif_sdram_config);
 	} else {
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 86c0e42174..e19c7aecec 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -19,7 +19,7 @@
 ENTRY(save_boot_params)
 	ldr	r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
 	str	r0, [r1]
-	bx	lr
+	b	save_boot_params_ret
 ENDPROC(save_boot_params)
 
 ENTRY(set_pl310_ctrl_reg)
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index a029379a4f..4a0ac2c987 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -93,6 +93,21 @@ config TARGET_TWISTER
 
 endchoice
 
+config DM
+	default y
+
+config DM_GPIO
+	default y if DM
+
+config DM_SERIAL
+	default y if DM
+
+config SYS_MALLOC_F
+	default y if DM
+
+config SYS_MALLOC_F_LEN
+	default 0x400 if DM
+
 config SYS_SOC
 	default "omap3"
 
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index 78577b1d1c..80cb2639f6 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -23,7 +23,7 @@ ENTRY(save_boot_params)
 	ldr	r5, [r0, #0x4]
 	and	r5, r5, #0xff
 	str	r5, [r4]
-	bx	lr
+	b	save_boot_params_ret
 ENDPROC(save_boot_params)
 #endif
 
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 7d8cec08c2..5f8daa1ee1 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -141,7 +141,8 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
 	.sdram_config_init              = 0x61851ab2,
 	.sdram_config                   = 0x61851ab2,
 	.sdram_config2			= 0x08000000,
-	.ref_ctrl                       = 0x00001035,
+	.ref_ctrl                       = 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
 	.sdram_tim1                     = 0xCCCF36B3,
 	.sdram_tim2                     = 0x308F7FDA,
 	.sdram_tim3                     = 0x027F88A8,
@@ -151,10 +152,10 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
 	.emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
 	.emif_ddr_phy_ctlr_1            = 0x0E24400A,
 	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
-	.emif_ddr_ext_phy_ctrl_2        = 0x00BB00BB,
-	.emif_ddr_ext_phy_ctrl_3        = 0x00BB00BB,
-	.emif_ddr_ext_phy_ctrl_4        = 0x00BB00BB,
-	.emif_ddr_ext_phy_ctrl_5        = 0x00BB00BB,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
 	.emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 	.emif_rd_wr_lvl_ctl             = 0x00000000,
@@ -165,7 +166,8 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
 	.sdram_config_init              = 0x61851B32,
 	.sdram_config                   = 0x61851B32,
 	.sdram_config2			= 0x08000000,
-	.ref_ctrl                       = 0x00001035,
+	.ref_ctrl                       = 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
 	.sdram_tim1                     = 0xCCCF36B3,
 	.sdram_tim2                     = 0x308F7FDA,
 	.sdram_tim3                     = 0x027F88A8,
@@ -175,10 +177,10 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
 	.emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
 	.emif_ddr_phy_ctlr_1            = 0x0E24400A,
 	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
-	.emif_ddr_ext_phy_ctrl_2        = 0x00BB00BB,
-	.emif_ddr_ext_phy_ctrl_3        = 0x00BB00BB,
-	.emif_ddr_ext_phy_ctrl_4        = 0x00BB00BB,
-	.emif_ddr_ext_phy_ctrl_5        = 0x00BB00BB,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
 	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
 	.emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 	.emif_rd_wr_lvl_ctl             = 0x00000000,
@@ -186,18 +188,19 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
 };
 
 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
-	.sdram_config_init              = 0x61851AB2,
-	.sdram_config                   = 0x61851AB2,
+	.sdram_config_init              = 0x61862B32,
+	.sdram_config                   = 0x61862B32,
 	.sdram_config2			= 0x08000000,
-	.ref_ctrl                       = 0x00001035,
-	.sdram_tim1                     = 0xCCCF36B3,
-	.sdram_tim2                     = 0x308F7FDA,
-	.sdram_tim3                     = 0x027F88A8,
+	.ref_ctrl                       = 0x0000493E,
+	.ref_ctrl_final			= 0x0000144A,
+	.sdram_tim1                     = 0xD113781C,
+	.sdram_tim2                     = 0x308F7FE3,
+	.sdram_tim3                     = 0x009F86A8,
 	.read_idle_ctrl                 = 0x00050000,
 	.zq_config                      = 0x0007190B,
 	.temp_alert_config              = 0x00000000,
-	.emif_ddr_phy_ctlr_1_init       = 0x0024400A,
-	.emif_ddr_phy_ctlr_1            = 0x0024400A,
+	.emif_ddr_phy_ctlr_1_init       = 0x0E24400D,
+	.emif_ddr_phy_ctlr_1            = 0x0E24400D,
 	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 	.emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
 	.emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
@@ -420,22 +423,22 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
-	0x00BB00BB,
-	0x00440044,
-	0x00440044,
-	0x00440044,
-	0x00440044,
-	0x00440044,
+	0x00980098,
+	0x00340034,
+	0x00350035,
+	0x00340034,
+	0x00310031,
+	0x00340034,
 	0x007F007F,
 	0x007F007F,
 	0x007F007F,
 	0x007F007F,
 	0x007F007F,
-	0x00600060,
-	0x00600060,
-	0x00600060,
-	0x00600060,
-	0x00600060,
+	0x00480048,
+	0x004A004A,
+	0x00520052,
+	0x00550055,
+	0x00500050,
 	0x00000000,
 	0x00600020,
 	0x40010080,
@@ -449,22 +452,22 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
 
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
-	0x00BB00BB,
-	0x00440044,
-	0x00440044,
-	0x00440044,
-	0x00440044,
-	0x00440044,
+	0x00980098,
+	0x00330033,
+	0x00330033,
+	0x002F002F,
+	0x00320032,
+	0x00310031,
 	0x007F007F,
 	0x007F007F,
 	0x007F007F,
 	0x007F007F,
 	0x007F007F,
-	0x00600060,
-	0x00600060,
-	0x00600060,
-	0x00600060,
-	0x00600060,
+	0x00520052,
+	0x00520052,
+	0x00470047,
+	0x00490049,
+	0x00500050,
 	0x00000000,
 	0x00600020,
 	0x40010080,
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig
index 6d94199de8..35866508a3 100644
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ b/arch/arm/cpu/armv7/rmobile/Kconfig
@@ -21,6 +21,9 @@ config TARGET_KZM9G
 config TARGET_ALT
 	bool "Alt board"
 
+config TARGET_SILK
+	bool "Silk board"
+
 endchoice
 
 config SYS_SOC
@@ -28,7 +31,7 @@ config SYS_SOC
 
 config RMOBILE_EXTRAM_BOOT
 	bool "Enable boot from RAM"
-	depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER
+	depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK
 	default n
 
 source "board/atmark-techno/armadillo-800eva/Kconfig"
@@ -37,5 +40,6 @@ source "board/renesas/koelsch/Kconfig"
 source "board/renesas/lager/Kconfig"
 source "board/kmc/kzm9g/Kconfig"
 source "board/renesas/alt/Kconfig"
+source "board/renesas/silk/Kconfig"
 
 endif
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
index d47546a11d..a5dbbea9e1 100644
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
@@ -40,7 +40,7 @@ do_lowlevel_init:
 	and	r1, r1, #0x7F00
 	lsrs	r1, r1, #8
 	cmp	r1, #0x4C		/* 0x4C is ID of r8a7794 */
-	beq	_exit_init_l2_a15
+	beq	_enable_actlr_smp
 
 	/* surpress wfe if ca15 */
 	tst r4, #4
@@ -64,6 +64,16 @@ do_lowlevel_init:
 	orrne r0, r0, #0x20		/* L2CTLR[5] */
 #endif
 	mcrne p15, 1, r0, c9, c0, 2
+
+	b	_exit_init_l2_a15
+
+_enable_actlr_smp: /* R8A7794 only (CA7) */
+#ifndef CONFIG_DCACHE_OFF
+	mrc    p15, 0, r0, c1, c0, 1
+	orr    r0, r0, #0x40
+	mcr    p15, 0, r0, c1, c0, 1
+#endif
+
 _exit_init_l2_a15:
 	ldr	r3, =(CONFIG_SYS_INIT_SP_ADDR)
 	sub	sp, r3, #4
diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig
index 628813423f..bc73813832 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig
+++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig
@@ -5,11 +5,11 @@ choice
 
 config TARGET_S5P_GONI
 	bool "S5P Goni board"
-	select OF_CONTROL if !SPL_BUILD
+	select OF_CONTROL
 
 config TARGET_SMDKC100
 	bool "Support smdkc100 board"
-	select OF_CONTROL if !SPL_BUILD
+	select OF_CONTROL
 
 endchoice
 
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 70048c10ae..9b49ece2d6 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -31,9 +31,12 @@
  *************************************************************************/
 
 	.globl	reset
+	.globl	save_boot_params_ret
 
 reset:
-	bl	save_boot_params
+	/* Allow the board to save important registers */
+	b	save_boot_params
+save_boot_params_ret:
 	/*
 	 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
 	 * except if in HYP mode already
@@ -96,7 +99,7 @@ ENDPROC(c_runtime_cpu_setup)
  *
  *************************************************************************/
 ENTRY(save_boot_params)
-	bx	lr			@ back to my caller
+	b	save_boot_params_ret		@ back to my caller
 ENDPROC(save_boot_params)
 	.weak	save_boot_params
 
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 48db7442f4..4bb12ad8bd 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-y	+= timer.o
 obj-y	+= board.o
 obj-y	+= clock.o
 obj-y	+= cpu_info.o
+obj-y	+= dram_helpers.o
 obj-y	+= pinmux.o
 obj-y	+= usbc.o
 obj-$(CONFIG_MACH_SUN6I)	+= prcm.o
@@ -38,7 +39,5 @@ obj-$(CONFIG_MACH_SUN5I)	+= dram_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)	+= dram_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)	+= dram_sun4i.o
 obj-$(CONFIG_MACH_SUN8I)	+= dram_sun8i.o
-ifdef CONFIG_SPL_FEL
-obj-y	+= start.o
-endif
+obj-y	+= fel_utils.o
 endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 6e28bcd040..c02c015096 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -27,6 +27,17 @@
 
 #include <linux/compiler.h>
 
+struct fel_stash {
+	uint32_t sp;
+	uint32_t lr;
+	uint32_t cpsr;
+	uint32_t sctlr;
+	uint32_t vbar;
+	uint32_t cr;
+};
+
+struct fel_stash fel_stash __attribute__((section(".data")));
+
 static int gpio_init(void)
 {
 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
@@ -65,6 +76,12 @@ static int gpio_init(void)
 	return 0;
 }
 
+void spl_board_load_image(void)
+{
+	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
+	return_to_fel(fel_stash.sp, fel_stash.lr);
+}
+
 void s_init(void)
 {
 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
@@ -95,7 +112,34 @@ void s_init(void)
  */
 u32 spl_boot_device(void)
 {
-	return BOOT_DEVICE_MMC1;
+#ifdef CONFIG_SPL_FEL
+	/*
+	 * This is the legacy compile time configuration for a special FEL
+	 * enabled build. It has many restrictions and can only boot over USB.
+	 */
+	return BOOT_DEVICE_BOARD;
+#else
+	/*
+	 * When booting from the SD card, the "eGON.BT0" signature is expected
+	 * to be found in memory at the address 0x0004 (see the "mksunxiboot"
+	 * tool, which generates this header).
+	 *
+	 * When booting in the FEL mode over USB, this signature is patched in
+	 * memory and replaced with something else by the 'fel' tool. This other
+	 * signature is selected in such a way, that it can't be present in a
+	 * valid bootable SD card image (because the BROM would refuse to
+	 * execute the SPL in this case).
+	 *
+	 * This branch is just making a decision at runtime whether to load
+	 * the main u-boot binary from the SD card (if the "eGON.BT0" signature
+	 * is found) or return to the FEL code in the BROM to wait and receive
+	 * the main u-boot binary over USB.
+	 */
+	if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */
+		return BOOT_DEVICE_MMC1;
+	else
+		return BOOT_DEVICE_BOARD;
+#endif
 }
 
 /* No confirmation data available in SPL yet. Hardcode bootmode */
diff --git a/arch/arm/cpu/armv7/sunxi/config.mk b/arch/arm/cpu/armv7/sunxi/config.mk
index 00f5ffc683..76ffec9df6 100644
--- a/arch/arm/cpu/armv7/sunxi/config.mk
+++ b/arch/arm/cpu/armv7/sunxi/config.mk
@@ -1,8 +1,6 @@
 # Build a combined spl + u-boot image
 ifdef CONFIG_SPL
 ifndef CONFIG_SPL_BUILD
-ifndef CONFIG_SPL_FEL
 ALL-y += u-boot-sunxi-with-spl.bin
 endif
 endif
-endif
diff --git a/arch/arm/cpu/armv7/sunxi/dram_helpers.c b/arch/arm/cpu/armv7/sunxi/dram_helpers.c
new file mode 100644
index 0000000000..9a94e1b679
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/dram_helpers.c
@@ -0,0 +1,37 @@
+/*
+ * DRAM init helper functions
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/dram.h>
+
+/*
+ * Wait up to 1s for value to be set in given part of reg.
+ */
+void mctl_await_completion(u32 *reg, u32 mask, u32 val)
+{
+	unsigned long tmo = timer_get_us() + 1000000;
+
+	while ((readl(reg) & mask) != val) {
+		if (timer_get_us() > tmo)
+			panic("Timeout initialising DRAM\n");
+	}
+}
+
+/*
+ * Test if memory at offset offset matches memory at begin of DRAM
+ */
+bool mctl_mem_matches(u32 offset)
+{
+	/* Try to write different values to RAM at two addresses */
+	writel(0, CONFIG_SYS_SDRAM_BASE);
+	writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset);
+	/* Check if the same value is actually observed when reading back */
+	return readl(CONFIG_SYS_SDRAM_BASE) ==
+	       readl(CONFIG_SYS_SDRAM_BASE + offset);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/fel_utils.S b/arch/arm/cpu/armv7/sunxi/fel_utils.S
new file mode 100644
index 0000000000..bf0033552d
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/fel_utils.S
@@ -0,0 +1,42 @@
+/*
+ * Utility functions for FEL mode.
+ *
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+	ldr	r0, =fel_stash
+	str	sp, [r0, #0]
+	str	lr, [r0, #4]
+	mrs	lr, cpsr		@ Read CPSR
+	str	lr, [r0, #8]
+	mrc	p15, 0, lr, c1, c0, 0	@ Read CP15 SCTLR Register
+	str	lr, [r0, #12]
+	mrc	p15, 0, lr, c12, c0, 0	@ Read VBAR
+	str	lr, [r0, #16]
+	mrc	p15, 0, lr, c1, c0, 0	@ Read CP15 Control Register
+	str	lr, [r0, #20]
+	b	save_boot_params_ret
+ENDPROC(save_boot_params)
+
+ENTRY(return_to_fel)
+	mov	sp, r0
+	mov	lr, r1
+	ldr	r0, =fel_stash
+	ldr	r1, [r0, #20]
+	mcr	p15, 0, r1, c1, c0, 0	@ Write CP15 Control Register
+	ldr	r1, [r0, #16]
+	mcr	p15, 0, r1, c12, c0, 0	@ Write VBAR
+	ldr	r1, [r0, #12]
+	mcr	p15, 0, r1, c1, c0, 0	@ Write CP15 SCTLR Register
+	ldr	r1, [r0, #8]
+	msr	cpsr, r1		@ Write CPSR
+	bx	lr
+ENDPROC(return_to_fel)
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
deleted file mode 100644
index 928b7c19e0..0000000000
--- a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * (C) Copyright 2013
- * Henrik Nordstrom <henrik@henriknordstrom.net>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(s_init)
-SECTIONS
-{
-	. = 0x00002000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		*(.text.s_init)
-		*(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data*)
-	}
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN(4);
-	. = .;
-
-	. = ALIGN(4);
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	. = ALIGN(4);
-	.note.gnu.build-id :
-	{
-		*(.note.gnu.build-id)
-	}
-	_end = .;
-
-	. = ALIGN(4096);
-	.mmutable : {
-		*(.mmutable)
-	}
-
-	.bss_start __rel_dyn_start (OVERLAY) : {
-		KEEP(*(.__bss_start));
-		__bss_base = .;
-	}
-
-	.bss __bss_base (OVERLAY) : {
-		*(.bss*)
-		. = ALIGN(4);
-		__bss_limit = .;
-	}
-
-	.bss_end __bss_limit (OVERLAY) : {
-		KEEP(*(.__bss_end));
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-	/DISCARD/ : { *(.note*) }
-}
diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig
deleted file mode 100644
index 1446452c23..0000000000
--- a/arch/arm/cpu/armv7/tegra-common/Kconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-if TEGRA
-
-choice
-	prompt "Tegra SoC select"
-
-config TEGRA20
-	bool "Tegra20 family"
-
-config TEGRA30
-	bool "Tegra30 family"
-
-config TEGRA114
-	bool "Tegra114 family"
-
-config TEGRA124
-	bool "Tegra124 family"
-
-endchoice
-
-config USE_PRIVATE_LIBGCC
-	default y if SPL_BUILD
-
-source "arch/arm/cpu/armv7/tegra20/Kconfig"
-source "arch/arm/cpu/armv7/tegra30/Kconfig"
-source "arch/arm/cpu/armv7/tegra114/Kconfig"
-source "arch/arm/cpu/armv7/tegra124/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/tegra-common/Makefile b/arch/arm/cpu/armv7/tegra-common/Makefile
deleted file mode 100644
index 463c260f18..0000000000
--- a/arch/arm/cpu/armv7/tegra-common/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
diff --git a/arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c b/arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c
deleted file mode 100644
index a94ec93e7b..0000000000
--- a/arch/arm/cpu/armv7/tegra-common/cmd_enterrcm.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * Derived from code (arch/arm/lib/reset.c) that is:
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * (C) Copyright 2004 Texas Insturments
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch-tegra/pmc.h>
-
-static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
-		       char * const argv[])
-{
-	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
-
-	puts("Entering RCM...\n");
-	udelay(50000);
-
-	pmc->pmc_scratch0 = 2;
-	disable_interrupts();
-	reset_cpu(0);
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	enterrcm, 1, 0, do_enterrcm,
-	"reset Tegra and enter USB Recovery Mode",
-	""
-);
diff --git a/arch/arm/cpu/armv7/tegra114/Kconfig b/arch/arm/cpu/armv7/tegra114/Kconfig
deleted file mode 100644
index 31012bc770..0000000000
--- a/arch/arm/cpu/armv7/tegra114/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TEGRA114
-
-choice
-	prompt "Tegra114 board select"
-
-config TARGET_DALMORE
-	bool "NVIDIA Tegra114 Dalmore evaluation board"
-
-endchoice
-
-config SYS_SOC
-	default "tegra114"
-
-source "board/nvidia/dalmore/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/tegra124/Kconfig b/arch/arm/cpu/armv7/tegra124/Kconfig
deleted file mode 100644
index 88f627c932..0000000000
--- a/arch/arm/cpu/armv7/tegra124/Kconfig
+++ /dev/null
@@ -1,30 +0,0 @@
-if TEGRA124
-
-choice
-	prompt "Tegra124 board select"
-
-config TARGET_JETSON_TK1
-	bool "NVIDIA Tegra124 Jetson TK1 board"
-
-config TARGET_NYAN_BIG
-	bool "Google/NVIDIA Nyan-big Chrombook"
-	help
-	  Nyan Big is a Tegra124 clamshell board that is very similar
-	  to venice2, but it has a different panel, the sdcard CD and WP
-	  sense are flipped, and it has a different revision of the AS3722
-	  PMIC. The retail name is the Acer Chromebook 13 CB5-311-T7NN
-	  (13.3-inch HD, NVIDIA Tegra K1, 2GB).
-
-config TARGET_VENICE2
-	bool "NVIDIA Tegra124 Venice2"
-
-endchoice
-
-config SYS_SOC
-	default "tegra124"
-
-source "board/nvidia/jetson-tk1/Kconfig"
-source "board/nvidia/nyan-big/Kconfig"
-source "board/nvidia/venice2/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/tegra20/Kconfig b/arch/arm/cpu/armv7/tegra20/Kconfig
deleted file mode 100644
index a354e2ad1f..0000000000
--- a/arch/arm/cpu/armv7/tegra20/Kconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-if TEGRA20
-
-choice
-	prompt "Tegra20 board select"
-
-config TARGET_HARMONY
-	bool "NVIDIA Tegra20 Harmony evaluation board"
-
-config TARGET_MEDCOM_WIDE
-	bool "Avionic Design Medcom-Wide board"
-
-config TARGET_PAZ00
-	bool "Paz00 board"
-
-config TARGET_PLUTUX
-	bool "Avionic Design Plutux board"
-
-config TARGET_SEABOARD
-	bool "NVIDIA Seaboard"
-
-config TARGET_TEC
-	bool "Avionic Design Tamonten Evaluation Carrier"
-
-config TARGET_TRIMSLICE
-	bool "Compulab TrimSlice board"
-
-config TARGET_VENTANA
-	bool "NVIDIA Tegra20 Ventana evaluation board"
-
-config TARGET_WHISTLER
-	bool "NVIDIA Tegra20 Whistler evaluation board"
-
-config TARGET_COLIBRI_T20_IRIS
-	bool "Toradex Colibri T20 board"
-
-endchoice
-
-config SYS_SOC
-	default "tegra20"
-
-source "board/nvidia/harmony/Kconfig"
-source "board/avionic-design/medcom-wide/Kconfig"
-source "board/compal/paz00/Kconfig"
-source "board/avionic-design/plutux/Kconfig"
-source "board/nvidia/seaboard/Kconfig"
-source "board/avionic-design/tec/Kconfig"
-source "board/compulab/trimslice/Kconfig"
-source "board/nvidia/ventana/Kconfig"
-source "board/nvidia/whistler/Kconfig"
-source "board/toradex/colibri_t20_iris/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/tegra20/Makefile b/arch/arm/cpu/armv7/tegra20/Makefile
deleted file mode 100644
index 9b4295c72d..0000000000
--- a/arch/arm/cpu/armv7/tegra20/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2010,2011 Nvidia Corporation.
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-$(CONFIG_PWM_TEGRA) += pwm.o
-obj-$(CONFIG_VIDEO_TEGRA) += display.o
diff --git a/arch/arm/cpu/armv7/tegra20/display.c b/arch/arm/cpu/armv7/tegra20/display.c
deleted file mode 100644
index 61efed6464..0000000000
--- a/arch/arm/cpu/armv7/tegra20/display.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- *  (C) Copyright 2010
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/tegra.h>
-#include <asm/arch/display.h>
-#include <asm/arch/dc.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/timer.h>
-
-static struct fdt_disp_config config;
-
-static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win)
-{
-	unsigned h_dda, v_dda;
-	unsigned long val;
-
-	val = readl(&dc->cmd.disp_win_header);
-	val |= WINDOW_A_SELECT;
-	writel(val, &dc->cmd.disp_win_header);
-
-	writel(win->fmt, &dc->win.color_depth);
-
-	clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK,
-			BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT);
-
-	val = win->out_x << H_POSITION_SHIFT;
-	val |= win->out_y << V_POSITION_SHIFT;
-	writel(val, &dc->win.pos);
-
-	val = win->out_w << H_SIZE_SHIFT;
-	val |= win->out_h << V_SIZE_SHIFT;
-	writel(val, &dc->win.size);
-
-	val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT;
-	val |= win->h << V_PRESCALED_SIZE_SHIFT;
-	writel(val, &dc->win.prescaled_size);
-
-	writel(0, &dc->win.h_initial_dda);
-	writel(0, &dc->win.v_initial_dda);
-
-	h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U);
-	v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U);
-
-	val = h_dda << H_DDA_INC_SHIFT;
-	val |= v_dda << V_DDA_INC_SHIFT;
-	writel(val, &dc->win.dda_increment);
-
-	writel(win->stride, &dc->win.line_stride);
-	writel(0, &dc->win.buf_stride);
-
-	val = WIN_ENABLE;
-	if (win->bpp < 24)
-		val |= COLOR_EXPAND;
-	writel(val, &dc->win.win_opt);
-
-	writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr);
-	writel(win->x, &dc->winbuf.addr_h_offset);
-	writel(win->y, &dc->winbuf.addr_v_offset);
-
-	writel(0xff00, &dc->win.blend_nokey);
-	writel(0xff00, &dc->win.blend_1win);
-
-	val = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
-	val |= GENERAL_UPDATE | WIN_A_UPDATE;
-	writel(val, &dc->cmd.state_ctrl);
-}
-
-static void write_pair(struct fdt_disp_config *config, int item, u32 *reg)
-{
-	writel(config->horiz_timing[item] |
-			(config->vert_timing[item] << 16), reg);
-}
-
-static int update_display_mode(struct dc_disp_reg *disp,
-		struct fdt_disp_config *config)
-{
-	unsigned long val;
-	unsigned long rate;
-	unsigned long div;
-
-	writel(0x0, &disp->disp_timing_opt);
-	write_pair(config, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync);
-	write_pair(config, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width);
-	write_pair(config, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch);
-	write_pair(config, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch);
-
-	writel(config->width | (config->height << 16), &disp->disp_active);
-
-	val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT;
-	val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT;
-	writel(val, &disp->data_enable_opt);
-
-	val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT;
-	val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT;
-	val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT;
-	writel(val, &disp->disp_interface_ctrl);
-
-	/*
-	 * The pixel clock divider is in 7.1 format (where the bottom bit
-	 * represents 0.5). Here we calculate the divider needed to get from
-	 * the display clock (typically 600MHz) to the pixel clock. We round
-	 * up or down as requried.
-	 */
-	rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL);
-	div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2;
-	debug("Display clock %lu, divider %lu\n", rate, div);
-
-	writel(0x00010001, &disp->shift_clk_opt);
-
-	val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT;
-	val |= div << SHIFT_CLK_DIVIDER_SHIFT;
-	writel(val, &disp->disp_clk_ctrl);
-
-	return 0;
-}
-
-/* Start up the display and turn on power to PWMs */
-static void basic_init(struct dc_cmd_reg *cmd)
-{
-	u32 val;
-
-	writel(0x00000100, &cmd->gen_incr_syncpt_ctrl);
-	writel(0x0000011a, &cmd->cont_syncpt_vsync);
-	writel(0x00000000, &cmd->int_type);
-	writel(0x00000000, &cmd->int_polarity);
-	writel(0x00000000, &cmd->int_mask);
-	writel(0x00000000, &cmd->int_enb);
-
-	val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE;
-	val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE;
-	val |= PM1_ENABLE;
-	writel(val, &cmd->disp_pow_ctrl);
-
-	val = readl(&cmd->disp_cmd);
-	val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
-	writel(val, &cmd->disp_cmd);
-}
-
-static void basic_init_timer(struct dc_disp_reg *disp)
-{
-	writel(0x00000020, &disp->mem_high_pri);
-	writel(0x00000001, &disp->mem_high_pri_timer);
-}
-
-static const u32 rgb_enb_tab[PIN_REG_COUNT] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const u32 rgb_polarity_tab[PIN_REG_COUNT] = {
-	0x00000000,
-	0x01000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const u32 rgb_data_tab[PIN_REG_COUNT] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-};
-
-static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = {
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00210222,
-	0x00002200,
-	0x00020000,
-};
-
-static void rgb_enable(struct dc_com_reg *com)
-{
-	int i;
-
-	for (i = 0; i < PIN_REG_COUNT; i++) {
-		writel(rgb_enb_tab[i], &com->pin_output_enb[i]);
-		writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]);
-		writel(rgb_data_tab[i], &com->pin_output_data[i]);
-	}
-
-	for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++)
-		writel(rgb_sel_tab[i], &com->pin_output_sel[i]);
-}
-
-static int setup_window(struct disp_ctl_win *win,
-			struct fdt_disp_config *config)
-{
-	win->x = 0;
-	win->y = 0;
-	win->w = config->width;
-	win->h = config->height;
-	win->out_x = 0;
-	win->out_y = 0;
-	win->out_w = config->width;
-	win->out_h = config->height;
-	win->phys_addr = config->frame_buffer;
-	win->stride = config->width * (1 << config->log2_bpp) / 8;
-	debug("%s: depth = %d\n", __func__, config->log2_bpp);
-	switch (config->log2_bpp) {
-	case 5:
-	case 24:
-		win->fmt = COLOR_DEPTH_R8G8B8A8;
-		win->bpp = 32;
-		break;
-	case 4:
-		win->fmt = COLOR_DEPTH_B5G6R5;
-		win->bpp = 16;
-		break;
-
-	default:
-		debug("Unsupported LCD bit depth");
-		return -1;
-	}
-
-	return 0;
-}
-
-struct fdt_disp_config *tegra_display_get_config(void)
-{
-	return config.valid ? &config : NULL;
-}
-
-static void debug_timing(const char *name, unsigned int timing[])
-{
-#ifdef DEBUG
-	int i;
-
-	debug("%s timing: ", name);
-	for (i = 0; i < FDT_LCD_TIMING_COUNT; i++)
-		debug("%d ", timing[i]);
-	debug("\n");
-#endif
-}
-
-/**
- * Decode panel information from the fdt, according to a standard binding
- *
- * @param blob		fdt blob
- * @param node		offset of fdt node to read from
- * @param config	structure to store fdt config into
- * @return 0 if ok, -ve on error
- */
-static int tegra_decode_panel(const void *blob, int node,
-			      struct fdt_disp_config *config)
-{
-	int front, back, ref;
-
-	config->width = fdtdec_get_int(blob, node, "xres", -1);
-	config->height = fdtdec_get_int(blob, node, "yres", -1);
-	config->pixel_clock = fdtdec_get_int(blob, node, "clock", 0);
-	if (!config->pixel_clock || config->width == -1 ||
-			config->height == -1) {
-		debug("%s: Pixel parameters missing\n", __func__);
-		return -FDT_ERR_NOTFOUND;
-	}
-
-	back = fdtdec_get_int(blob, node, "left-margin", -1);
-	front = fdtdec_get_int(blob, node, "right-margin", -1);
-	ref = fdtdec_get_int(blob, node, "hsync-len", -1);
-	if ((back | front | ref) == -1) {
-		debug("%s: Horizontal parameters missing\n", __func__);
-		return -FDT_ERR_NOTFOUND;
-	}
-
-	/* Use a ref-to-sync of 1 always, and take this from the front porch */
-	config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
-	config->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
-	config->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
-	config->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
-		config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC];
-	debug_timing("horiz", config->horiz_timing);
-
-	back = fdtdec_get_int(blob, node, "upper-margin", -1);
-	front = fdtdec_get_int(blob, node, "lower-margin", -1);
-	ref = fdtdec_get_int(blob, node, "vsync-len", -1);
-	if ((back | front | ref) == -1) {
-		debug("%s: Vertical parameters missing\n", __func__);
-		return -FDT_ERR_NOTFOUND;
-	}
-
-	config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1;
-	config->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref;
-	config->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back;
-	config->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front -
-		config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC];
-	debug_timing("vert", config->vert_timing);
-
-	return 0;
-}
-
-/**
- * Decode the display controller information from the fdt.
- *
- * @param blob		fdt blob
- * @param config	structure to store fdt config into
- * @return 0 if ok, -ve on error
- */
-static int tegra_display_decode_config(const void *blob,
-				       struct fdt_disp_config *config)
-{
-	int node, rgb;
-	int bpp, bit;
-
-	/* TODO: Support multiple controllers */
-	node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_DC);
-	if (node < 0) {
-		debug("%s: Cannot find display controller node in fdt\n",
-		      __func__);
-		return node;
-	}
-	config->disp = (struct disp_ctlr *)fdtdec_get_addr(blob, node, "reg");
-	if (!config->disp) {
-		debug("%s: No display controller address\n", __func__);
-		return -1;
-	}
-
-	rgb = fdt_subnode_offset(blob, node, "rgb");
-
-	config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel");
-	if (config->panel_node < 0) {
-		debug("%s: Cannot find panel information\n", __func__);
-		return -1;
-	}
-
-	if (tegra_decode_panel(blob, config->panel_node, config)) {
-		debug("%s: Failed to decode panel information\n", __func__);
-		return -1;
-	}
-
-	bpp = fdtdec_get_int(blob, config->panel_node, "nvidia,bits-per-pixel",
-			     -1);
-	bit = ffs(bpp) - 1;
-	if (bpp == (1 << bit))
-		config->log2_bpp = bit;
-	else
-		config->log2_bpp = bpp;
-	if (bpp == -1) {
-		debug("%s: Pixel bpp parameters missing\n", __func__);
-		return -FDT_ERR_NOTFOUND;
-	}
-	config->bpp = bpp;
-
-	config->valid = 1;	/* we have a valid configuration */
-
-	return 0;
-}
-
-int tegra_display_probe(const void *blob, void *default_lcd_base)
-{
-	struct disp_ctl_win window;
-	struct dc_ctlr *dc;
-
-	if (tegra_display_decode_config(blob, &config))
-		return -1;
-
-	config.frame_buffer = (u32)default_lcd_base;
-
-	dc = (struct dc_ctlr *)config.disp;
-
-	/*
-	 * A header file for clock constants was NAKed upstream.
-	 * TODO: Put this into the FDT and fdt_lcd struct when we have clock
-	 * support there
-	 */
-	clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH,
-			       144 * 1000000);
-	clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL,
-			       600 * 1000000);
-	basic_init(&dc->cmd);
-	basic_init_timer(&dc->disp);
-	rgb_enable(&dc->com);
-
-	if (config.pixel_clock)
-		update_display_mode(&dc->disp, &config);
-
-	if (setup_window(&window, &config))
-		return -1;
-
-	update_window(dc, &window);
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/tegra20/pwm.c b/arch/arm/cpu/armv7/tegra20/pwm.c
deleted file mode 100644
index 5b886363f8..0000000000
--- a/arch/arm/cpu/armv7/tegra20/pwm.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Tegra2 pulse width frequency modulator definitions
- *
- * Copyright (c) 2011 The Chromium OS Authors.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <fdtdec.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/pwm.h>
-
-struct pwm_info {
-	struct pwm_ctlr *pwm;		/* Registers for our pwm controller */
-	int pwm_node;			/* PWM device tree node */
-} local;
-
-void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider)
-{
-	u32 reg;
-
-	assert(channel < PWM_NUM_CHANNELS);
-
-	/* TODO: Can we use clock_adjust_periph_pll_div() here? */
-	clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, rate);
-
-	reg = PWM_ENABLE_MASK;
-	reg |= pulse_width << PWM_WIDTH_SHIFT;
-	reg |= freq_divider << PWM_DIVIDER_SHIFT;
-	writel(reg, &local.pwm[channel].control);
-	debug("%s: channel=%d, rate=%d\n", __func__, channel, rate);
-}
-
-int pwm_request(const void *blob, int node, const char *prop_name)
-{
-	int pwm_node;
-	u32 data[3];
-
-	if (fdtdec_get_int_array(blob, node, prop_name, data,
-			ARRAY_SIZE(data))) {
-		debug("%s: Cannot decode PWM property '%s'\n", __func__,
-		      prop_name);
-		return -1;
-	}
-
-	pwm_node = fdt_node_offset_by_phandle(blob, data[0]);
-	if (pwm_node != local.pwm_node) {
-		debug("%s: PWM property '%s' phandle %d not recognised"
-		      "- expecting %d\n", __func__, prop_name, data[0],
-		      local.pwm_node);
-		return -1;
-	}
-	if (data[1] >= PWM_NUM_CHANNELS) {
-		debug("%s: PWM property '%s': invalid channel %u\n", __func__,
-		      prop_name, data[1]);
-		return -1;
-	}
-
-	/*
-	 * TODO: We could maintain a list of requests, but it might not be
-	 * worth it for U-Boot.
-	 */
-	return data[1];
-}
-
-int pwm_init(const void *blob)
-{
-	local.pwm_node = fdtdec_next_compatible(blob, 0,
-						COMPAT_NVIDIA_TEGRA20_PWM);
-	if (local.pwm_node < 0) {
-		debug("%s: Cannot find device tree node\n", __func__);
-		return -1;
-	}
-
-	local.pwm = (struct pwm_ctlr *)fdtdec_get_addr(blob, local.pwm_node,
-						       "reg");
-	if (local.pwm == (struct pwm_ctlr *)FDT_ADDR_T_NONE) {
-		debug("%s: Cannot find pwm reg address\n", __func__);
-		return -1;
-	}
-	debug("Tegra PWM at %p, node %d\n", local.pwm, local.pwm_node);
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/tegra30/Kconfig b/arch/arm/cpu/armv7/tegra30/Kconfig
deleted file mode 100644
index 3abdc7ba17..0000000000
--- a/arch/arm/cpu/armv7/tegra30/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-if TEGRA30
-
-choice
-	prompt "Tegra30 board select"
-
-config TARGET_APALIS_T30
-	bool "Toradex Apalis T30 board"
-
-config TARGET_BEAVER
-	bool "NVIDIA Tegra30 Beaver evaluation board"
-
-config TARGET_CARDHU
-	bool "NVIDIA Tegra30 Cardhu evaluation board"
-
-config TARGET_COLIBRI_T30
-	bool "Toradex Colibri T30 board"
-
-config TARGET_TEC_NG
-	bool "Avionic Design TEC-NG board"
-
-endchoice
-
-config SYS_SOC
-	default "tegra30"
-
-source "board/toradex/apalis_t30/Kconfig"
-source "board/nvidia/beaver/Kconfig"
-source "board/nvidia/cardhu/Kconfig"
-source "board/toradex/colibri_t30/Kconfig"
-source "board/avionic-design/tec-ng/Kconfig"
-
-endif
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig
index 5c5a84fe56..8335685e32 100644
--- a/arch/arm/cpu/armv7/uniphier/Kconfig
+++ b/arch/arm/cpu/armv7/uniphier/Kconfig
@@ -48,6 +48,12 @@ config DCC_MICRO_SUPPORT_CARD
 
 endchoice
 
+config SYS_MALLOC_F
+	default y
+
+config SYS_MALLOC_F_LEN
+	default 0x400
+
 config CMD_PINMON
 	bool "Enable boot mode pins monitor command"
 	default y
@@ -58,14 +64,12 @@ config CMD_PINMON
 
 config CMD_DDRPHY_DUMP
 	bool "Enable dump command of DDR PHY parameters"
-	depends on !SPL_BUILD
 	help
 	  The command "ddrphy" shows the resulting parameters of DDR PHY
 	  training; it is useful for the evaluation of DDR PHY training.
 
 choice
 	prompt "DDR3 Frequency select"
-	depends on SPL_BUILD
 
 config DDR_FREQ_1600
 	bool "DDR3 1600"