diff options
| author | York Sun <yorksun@freescale.com> | 2015-11-04 10:03:22 -0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-12-13 18:27:28 -0800 |
| commit | c4243ac9e2713897a63dcdc3a96bf088fdb49866 (patch) | |
| tree | ff5766eef6dc2f238791a238bccbc484941373cc /arch/arm/cpu/armv7 | |
| parent | 6c6e006a2083f2da7b4f66c6bb82ce8b3fb713a3 (diff) | |
armv8/ls2080aqds: Update DDR settings for four chip-select case
When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
0 files changed, 0 insertions, 0 deletions