diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2015-06-23 19:57:25 +0800 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-07-05 11:32:11 +0200 |
| commit | e506889c9690b672a601ac84a31bb8dbc40d7e35 (patch) | |
| tree | df8c7297faa3552397ee941ddc8a8600a4527989 /arch/arm/cpu/armv7 | |
| parent | dec7c84227339cda4bf6c7d9a411ea189473112d (diff) | |
sunxi: Add support for UART0 in PB pin group on A33
The A33 adds a pinmux function for UART0 in the PB pin group.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/board.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 1c268656ff..5f39aa07cf 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -64,6 +64,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); |