diff options
author | Stephen Warren <swarren@nvidia.com> | 2015-10-05 12:09:00 -0600 |
---|---|---|
committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-11-10 18:03:41 +0100 |
commit | 3c6af3bad4f644e050f67146f4a6e177d5e39e76 (patch) | |
tree | fca74b95f921af67e2aba412d3ff697692756228 /arch/arm/cpu/armv8/cache_v8.c | |
parent | 88f965d720b745431a1fbe9107c561b7f381026c (diff) |
armv8: allow custom MMU setup routines on ARMv8
In order for noncached_init() to operate correctly, SoCs must set up a
custom page table with fine-grained (2MiB) sections, which can be
configured from noncached_init().
This is currently performed by arch/arm/cpu/armv8/{fsl-lsch3,zynqmp}/cpu.c
by cut/pasting and re-implementing mmu_setup, enable_caches(), etc. There
are some other reasons for the duplication there though, such as enabling
icache early, and enabling dcaching earlier with a different configuration.
This change makes mmu_setup() a weak implementation, so that the MMU setup
code can be replaced without having to duplicate other code that calls it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/armv8/cache_v8.c')
-rw-r--r-- | arch/arm/cpu/armv8/cache_v8.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index b1ea8227cb..1ece6a2c12 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -32,7 +32,7 @@ inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr) } /* to activate the MMU we need to set up virtual memory */ -static void mmu_setup(void) +__weak void mmu_setup(void) { bd_t *bd = gd->bd; u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j; |