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authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>2019-04-08 10:15:41 +0000
committerPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>2019-05-22 12:24:24 +0530
commit059d942283eb79bad369dd66512a5135dff05f4d (patch)
tree527f2dc630c9d8220ea3590a7547469bb68550ca /arch/arm/cpu/armv8/fsl-layerscape/cpu.c
parent3fbe8f0f44aad82d7a32c37209e6dbed2a1171a3 (diff)
armv8: lx2160a: add MMU table entries for PCIe
The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/cpu.c')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index db7577b6ed..9801e64867 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -258,6 +258,20 @@ static struct mm_region final_map[] = {
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#endif
+#ifdef SYS_PCIE5_PHYS_ADDR
+ { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
+ SYS_PCIE5_PHYS_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+#endif
+#ifdef SYS_PCIE6_PHYS_ADDR
+ { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
+ SYS_PCIE6_PHYS_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+#endif
{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
CONFIG_SYS_FSL_WRIOP1_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |