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| author | Tom Rini <trini@konsulko.com> | 2017-05-26 11:19:27 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-05-26 11:19:27 -0400 |
| commit | 380e86f361e4e2aef83295972863654fde157560 (patch) | |
| tree | 5b1f04c1c763f6c06ae099a6eadac4eb2eb6d6b8 /arch/arm/cpu/armv8/fsl-layerscape/cpu.c | |
| parent | 8dc1b17f14c9201c7d0da0f33e404a7e051b2ec6 (diff) | |
| parent | 7676074ac756ab9566d52544cc836f7b93f80b37 (diff) | |
Merge git://git.denx.de/u-boot-fsl-qoriq
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/cpu.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index bb029608bf..cba0095e6a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1,4 +1,5 @@ /* + * Copyright 2017 NXP * Copyright 2014-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ @@ -98,7 +99,8 @@ static void fix_pcie_mmu_map(void) /* Fix PCIE base and size for LS2088A */ if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) || - (ver == SVR_LS2048A) || (ver == SVR_LS2044A)) { + (ver == SVR_LS2048A) || (ver == SVR_LS2044A) || + (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) { for (i = 0; i < ARRAY_SIZE(final_map); i++) { switch (final_map[i].phys) { case CONFIG_SYS_PCIE1_PHYS_ADDR: |