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| author | Tom Rini <trini@konsulko.com> | 2018-09-29 11:47:32 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-09-29 11:47:32 -0400 |
| commit | 27f622d56876f01e11a74b292e52a94451144cff (patch) | |
| tree | 65bc08481bdd26255de948e373e70707dd1e73ab /arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | |
| parent | 83f6f608c278d9ac3fda7d0bb05f41c06b397964 (diff) | |
| parent | 26cbc0d663555b8af7d40ecfd0d0fefe960d9686 (diff) | |
Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriq
Switch to driver model for eSDHC on Layerscape SoCs including LS1021A,
LS1043A, LS1046A, LS1088A, LS2088A.
Switch to driver model for SATA on LS1021A and LS1043A.
Add support for LS1012AFRWY rev C board.
Enable SMMU for LS1043A.
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 653c6dddca..bc268e207c 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -192,6 +192,16 @@ int get_dspi_freq(ulong dummy) return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV; } +#ifdef CONFIG_FSL_ESDHC +int get_sdhc_freq(ulong dummy) +{ + if (!gd->arch.sdhc_clk) + get_clocks(); + + return gd->arch.sdhc_clk; +} +#endif + int get_serial_clock(void) { return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; @@ -202,6 +212,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk) switch (clk) { case MXC_I2C_CLK: return get_i2c_freq(0); +#if defined(CONFIG_FSL_ESDHC) + case MXC_ESDHC_CLK: + return get_sdhc_freq(0); +#endif case MXC_DSPI_CLK: return get_dspi_freq(0); default: |