diff options
| author | Laurentiu Tudor <laurentiu.tudor@nxp.com> | 2019-02-26 13:18:33 +0200 |
|---|---|---|
| committer | Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | 2019-03-03 22:01:09 +0530 |
| commit | e82d9ee73a2ab6ae76999f4eb37807af7e38cdc0 (patch) | |
| tree | acb55c5951b623566bfc13b2d0793438004cc3f1 /arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | |
| parent | d8d5fdb7b2ab9154beee2936082bfb65bf4d9209 (diff) | |
armv8: fsl-layerscape: fix SEC QI ICID setup
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
ICIDs in order to share the isolation context.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c index 0e8649427e..3bd993bebf 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -43,7 +43,7 @@ struct icid_id_table icid_tbl[] = { SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID), SET_QE_ICID(FSL_QE_STREAM_ID), #ifdef CONFIG_FSL_CAAM - SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2), + SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_END), SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3), SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4), SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5), |