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| author | Ashish Kumar <Ashish.Kumar@nxp.com> | 2017-08-11 11:09:14 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-09-11 07:55:36 -0700 |
| commit | 63b2316c5c4ba0e47d1f69ef1372db4fd89b6bf5 (patch) | |
| tree | 065b8277ffa5951efbff0a53bdb8a6f797d7b884 /arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S | |
| parent | 584f316f115df52fd09a6cf699b29dcf824b4da5 (diff) | |
fsl-layerscape: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.
This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S')
0 files changed, 0 insertions, 0 deletions