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authorRan Wang <ran.wang_1@nxp.com>2019-11-26 11:40:40 +0800
committerPriyanka Jain <priyanka.jain@nxp.com>2019-12-26 16:00:20 +0530
commit0cfa00cdb94d5349e0d33fabe157caef667ab004 (patch)
tree97255f50eb303e1296f7f3a78c9b7fdf87ae702e /arch/arm/cpu/armv8/fsl-layerscape/soc.c
parent055aa33ff9576490fe5d39e693bf3c3a4f8bcd08 (diff)
armv8: Add workaround for USB erratum A-050106
USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar to erratum A-009007, but this one is for LX2160A, and the register value is different. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/soc.c')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/soc.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 70933a2e03..4b193c6091 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -147,7 +147,7 @@ static void erratum_a008997(void)
out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
- defined(CONFIG_ARCH_LS1028A)
+ defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
@@ -181,6 +181,15 @@ static void erratum_a009007(void)
}
#if defined(CONFIG_FSL_LSCH3)
+static void erratum_a050106(void)
+{
+#if defined(CONFIG_ARCH_LX2160A)
+ void __iomem *dcsr = (void __iomem *)DCSR_BASE;
+
+ PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
+ PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
+#endif
+}
/*
* This erratum requires setting a value to eddrtqcr1 to
* optimal the DDR performance.
@@ -332,6 +341,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009798();
erratum_a008997();
erratum_a009007();
+ erratum_a050106();
#ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.