diff options
| author | Priyanka Jain <priyanka.jain@nxp.com> | 2016-11-17 12:29:55 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-11-22 11:37:54 -0800 |
| commit | 9ae836cde7aa8f54ee06879b1653b7260f866629 (patch) | |
| tree | 1e094be0c4d2bfe76864856e26a359f1a919ae4d /arch/arm/cpu/armv8/fsl-layerscape/soc.c | |
| parent | d5df606d17f80d78e4d577e80fd0034dc66486be (diff) | |
armv8: fsl-layerscape: Add NXP LS2088A SoC support
The QorIQ LS2088A SoC is built on layerscape architecture.
It is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)It supports TZASC module
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 5a4dd39a61..6c4238707d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -31,8 +31,10 @@ bool soc_has_dp_ddr(void) struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 svr = gur_in32(&gur->svr); - /* LS2085A has DP_DDR */ - if (SVR_SOC_VER(svr) == SVR_LS2085A) + /* LS2085A, LS2088A, LS2048A has DP_DDR */ + if ((SVR_SOC_VER(svr) == SVR_LS2085A) || + (SVR_SOC_VER(svr) == SVR_LS2088A) || + (SVR_SOC_VER(svr) == SVR_LS2048A)) return true; return false; |