diff options
| author | York Sun <yorksun@freescale.com> | 2015-03-20 19:28:08 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-04-23 08:55:55 -0700 |
| commit | 207774b213caa3c72ebd6c9f6d1e4a3a666938b7 (patch) | |
| tree | b0249e1f667a1c607cc1409dfbe7db7fb9b62840 /arch/arm/cpu/armv8/fsl-lsch3/mp.c | |
| parent | 19f9175027b14f11b5a30df17ce76fb6f64dc724 (diff) | |
armv8/ls2085a: Fix generic timer clock source
The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Mark Rutland <mark.rutland@arm.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-lsch3/mp.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/mp.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-lsch3/mp.c index ce9c0c1bdb..da7853a5af 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c @@ -31,6 +31,13 @@ int fsl_lsch3_wake_seconday_cores(void) int i, timeout = 10; u64 *table = get_spin_tbl_addr(); +#ifdef COUNTER_FREQUENCY_REAL + /* update for secondary cores */ + __real_cntfrq = COUNTER_FREQUENCY_REAL; + flush_dcache_range((unsigned long)&__real_cntfrq, + (unsigned long)&__real_cntfrq + 8); +#endif + cores = cpu_mask(); /* Clear spin table so that secondary processors * observe the correct value after waking up from wfe. |