diff options
| author | York Sun <yorksun@freescale.com> | 2014-02-26 13:26:02 -0800 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-04-07 17:43:32 +0200 |
| commit | f5222cfd49bd3681008039e82aa7a1db3e6c9af4 (patch) | |
| tree | f7f81d3f14300d54b4f12125a56b8ce7f17339d4 /arch/arm/cpu/armv8/start.S | |
| parent | 2c67e0e7cfa750b006725d3a42f42d3926979b90 (diff) | |
armv8/cache: Consolidate setting for MAIR and TCR
Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with
sub-architecture.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>
Diffstat (limited to 'arch/arm/cpu/armv8/start.S')
| -rw-r--r-- | arch/arm/cpu/armv8/start.S | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index bcc2603098..90daa4d2fd 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -128,28 +128,6 @@ ENTRY(c_runtime_cpu_setup) isb sy #endif -#ifndef CONFIG_SYS_DCACHE_OFF - /* - * Setup MAIR and TCR. - */ - ldr x0, =MEMORY_ATTRIBUTES - ldr x1, =TCR_FLAGS - - switch_el x2, 3f, 2f, 1f -3: orr x1, x1, TCR_EL3_IPS_BITS - msr mair_el3, x0 - msr tcr_el3, x1 - b 0f -2: orr x1, x1, TCR_EL2_IPS_BITS - msr mair_el2, x0 - msr tcr_el2, x1 - b 0f -1: orr x1, x1, TCR_EL1_IPS_BITS - msr mair_el1, x0 - msr tcr_el1, x1 -0: -#endif - /* Relocate vBAR */ adr x0, vectors switch_el x1, 3f, 2f, 1f |