Merge tag 'xilinx-for-v2019.04' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2019.04

tools:
- Fix zynqmpimage generation

zynq:
- Some configs/Kconfig/DT updates
- Enable REMAKE_ELF and OF_SEPARATE
- Topic boards update
- i2c cleanups and conversion to DM_I2C

zynqmp:
- Some configs/Kconfig/DT updates
- Board config cleanup
- Move arch folder to mach-zynqmp

versal:
- Enable DM_I2C, CMD_DM

zynq-gem:
- Fix driver cache handling

i2c:
- Live tree simple update

phy:
- Fixed phy cleanup

travis:
- Wire Versal SoC

1 files changed, 0 insertions, 45 deletions

diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c
deleted file mode 100644
index 0593b6310f..0000000000
--- a/arch/arm/cpu/armv8/zynqmp/clk.c
+++ /dev/null
@@ -1,45 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2014 - 2015 Xilinx, Inc.
- * Michal Simek <michal.simek@xilinx.com>
- */
-
-#include <common.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-unsigned long zynqmp_get_system_timer_freq(void)
-{
-	u32 ver = zynqmp_get_silicon_version();
-
-	switch (ver) {
-	case ZYNQMP_CSU_VERSION_QEMU:
-		return 50000000;
-	}
-
-	return 100000000;
-}
-
-#ifdef CONFIG_CLOCKS
-/**
- * set_cpu_clk_info() - Initialize clock framework
- * Always returns zero.
- *
- * This function is called from common code after relocation and sets up the
- * clock framework. The framework must not be used before this function had been
- * called.
- */
-int set_cpu_clk_info(void)
-{
-	gd->cpu_clk = get_tbclk();
-
-	gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
-
-	gd->bd->bi_dsp_freq = 0;
-
-	return 0;
-}
-#endif