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| author | Tom Rini <trini@konsulko.com> | 2018-01-31 07:10:55 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-01-31 07:10:55 -0500 |
| commit | ab21ecef7a38dd211fe6db35c6e60800445eb6a2 (patch) | |
| tree | 88206942bc34bb97062d793e56db6f97cf74ea8f /arch/arm/cpu/armv8/zynqmp/cpu.c | |
| parent | 11d2e98d7e75dfb40651eb95c32ca36778cd96d3 (diff) | |
| parent | e7563c204eb4f7a422121c342e4e9f34cd1986e9 (diff) | |
Merge tag 'xilinx-for-v2018.03' of git://git.denx.de/u-boot-microblaze
Xilinx changes for v2018.03
- Several Kconfig fixes (also moving configs to defconfigs)
- Some DTS updates
- ZynqMP psu rework based on Zynq concept
- Add low level initialization for zc770 and zcu102
- Add support for Zynq zc770 x16 nand configuration
- Add mini nand/emmc ZynqMP targets
- Some arasan nand changes
Diffstat (limited to 'arch/arm/cpu/armv8/zynqmp/cpu.c')
| -rw-r--r-- | arch/arm/cpu/armv8/zynqmp/cpu.c | 28 |
1 files changed, 18 insertions, 10 deletions
diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index f026cb4511..bc77dd03c3 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -17,20 +17,24 @@ DECLARE_GLOBAL_DATA_PTR; static struct mm_region zynqmp_mem_map[] = { +#if !defined(CONFIG_ZYNQMP_NO_DDR) { .virt = 0x0UL, .phys = 0x0UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE - }, { + }, +#endif + { .virt = 0x80000000UL, .phys = 0x80000000UL, .size = 0x70000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { + }, + { .virt = 0xf8000000UL, .phys = 0xf8000000UL, .size = 0x07e00000UL, @@ -48,20 +52,24 @@ static struct mm_region zynqmp_mem_map[] = { #endif .virt = 0x400000000UL, .phys = 0x400000000UL, - .size = 0x200000000UL, + .size = 0x400000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x600000000UL, - .phys = 0x600000000UL, + }, +#if !defined(CONFIG_ZYNQMP_NO_DDR) + { + .virt = 0x800000000UL, + .phys = 0x800000000UL, .size = 0x800000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xe00000000UL, - .phys = 0xe00000000UL, - .size = 0xf200000000UL, + }, +#endif + { + .virt = 0x1000000000UL, + .phys = 0x1000000000UL, + .size = 0xf000000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN |