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| author | Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> | 2017-08-01 16:24:52 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2017-11-28 16:08:56 +0100 |
| commit | f322ad604e7e1418f8deb7646aa5d2b0a2bae83e (patch) | |
| tree | b606391076fa4b607c306a1e6711127e05d6ea9d /arch/arm/cpu/armv8/zynqmp/cpu.c | |
| parent | 62e950fad3cc8c9bee0d4499e580d4ff80945028 (diff) | |
arm64: zynqmp: mp: Correct the R5 release sequence
This patch corrects the R5 release sequence by adding the
below steps.
1. Flush dcache to ensure that image loaded into memory.
2. Keep R5 reset just to ensure R5 in reset.
3. Disable caches before accessing TCM as with out this
A53 can do speculative and may result in ECC failures
if TCM's are not initialized. So, it is always better
to disable dcaches before accessing TCM and enable back.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reported-by: John Linn <linnj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/cpu/armv8/zynqmp/cpu.c')
0 files changed, 0 insertions, 0 deletions