diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2016-08-11 13:00:59 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-08-12 09:23:47 -0400 |
| commit | 1f01962e0fde9d3e57318e9f6e05c45d8ef2a783 (patch) | |
| tree | 705a2495695397c838f8019a9651af4d344be202 /arch/arm/cpu/armv8 | |
| parent | 358133239b37cf3c936cc968d7bde9c5546ad130 (diff) | |
drivers: net: cpsw: always flush cache of size aligned to PKTALIGN
cpsw tries to flush dcache which is not in the range of PKTALIGN.
Because of this the following warning comes while flushing:
CACHE: Misaligned operation at range [dffecec0, dffed016]
Fix it by flushing cache of size aligned to PKTALIGN.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/cpu/armv8')
0 files changed, 0 insertions, 0 deletions