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| author | Stefano Babic <sbabic@denx.de> | 2016-05-17 17:51:44 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-05-17 17:51:44 +0200 |
| commit | 52b1eaf93d6b55e1467f97b8eefdc2f8b6031c43 (patch) | |
| tree | 73357539a8382b406c29b1826dc17012f267f2cb /arch/arm/cpu/armv8 | |
| parent | aaeadd3f7b248aeb1c72c36183ab9c6e77da6ce2 (diff) | |
| parent | aeaec0e682f45b9e0c62c522fafea353931f73ed (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'arch/arm/cpu/armv8')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/start.S | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index d580a43b41..a9b12a43ad 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -180,7 +180,7 @@ ulong get_ddr_freq(ulong ctrl_num) /* * DDR controller 0 & 1 are on memory complex 0 - * DDR controler 2 is on memory complext 1 + * DDR controller 2 is on memory complext 1 */ #ifdef CONFIG_SYS_FSL_HAS_DP_DDR if (ctrl_num >= 2) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index deb44a895f..c3cc8199ca 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -214,7 +214,9 @@ WEAK(lowlevel_init) ldr x1, =GICC_BASE bl gic_init_secure_percpu #endif +#endif +#ifndef CONFIG_ARMV8_MULTIENTRY branch_if_master x0, x1, 2f /* |