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authorYork Sun <york.sun@nxp.com>2018-11-05 18:01:23 +0000
committerYork Sun <york.sun@nxp.com>2018-12-06 14:37:19 -0800
commitbb50569dc4c3ac71af075d5e994d0a37579efc51 (patch)
treeab3f6f67e06a08a7d06725c7f29b8987e26936ba /arch/arm/cpu/armv8
parent088d52cfa8ec515316e20a6168dc2dd163c799b9 (diff)
armv8: layerscape: Enable routing SError exception
In case SError happens at EL2, if SCR_EL3[EA] is not routing it to EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes the exception to EL2. Otherwise this exception is not taken. Signed-off-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index ef3987ea84..11b5fb2ec3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -71,6 +71,15 @@ ENDPROC(smp_kick_all_cpus)
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
+ /* unmask SError and abort */
+ msr daifclr, #4
+
+ /* Set HCR_EL2[AMO] so SError @EL2 is taken */
+ mrs x0, hcr_el2
+ orr x0, x0, #0x20 /* AMO */
+ msr hcr_el2, x0
+ isb
+
switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
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