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authorAshish Kumar <Ashish.Kumar@nxp.com>2017-08-18 10:54:35 +0530
committerYork Sun <york.sun@nxp.com>2017-09-22 12:41:24 -0700
commitbdbcb522568fe46dc6141ea1f799e2d08b0e3d76 (patch)
treedd39f525f6558b3b007f5f92230f8ad7c2d0391c /arch/arm/cpu/armv8
parent88486d0423d3a58ce188fcf66e2b7a457acc39c2 (diff)
armv8: fsl-layerscape: Put SATA code under SATA configs
It is not necessary for every SoC to have 2 SATA controller. So put SATA1, SATA2 code under respective defines. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/soc.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6698c0467d..7e5a6baf59 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -323,11 +323,14 @@ int sata_init(void)
{
struct ccsr_ahci __iomem *ccsr_ahci;
+#ifdef CONFIG_SYS_SATA2
ccsr_ahci = (void *)CONFIG_SYS_SATA2;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
+#endif
+#ifdef CONFIG_SYS_SATA1
ccsr_ahci = (void *)CONFIG_SYS_SATA1;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
@@ -335,6 +338,7 @@ int sata_init(void)
ahci_init((void __iomem *)CONFIG_SYS_SATA1);
scsi_scan(false);
+#endif
return 0;
}