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authorPriyanka Jain <priyanka.jain@nxp.com>2016-11-09 12:27:54 +0530
committerYork Sun <york.sun@nxp.com>2017-01-18 09:23:49 -0800
commitd037261f7f36a8c1e56acb1a52480d945cbb6f63 (patch)
tree8e4b2c2b52504c8831a9b8f6fa4d08cc9b3ab535 /arch/arm/cpu/armv8
parent97205eeab4d1a785340052657673c56f2d440db7 (diff)
armv8: fsl-layerscape, ccn504: Set forced-order mode in RNI-6, RNI-20
It is recommended to set forced-order mode in RNI-6, RNI-20 for performance optimization in LS2088A. Both LS2080A, LS2088A families has CONFIG_LS2080A define. As above update is required only for LS2088A, skip this for LS2080A SoC family. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 72f2c11baf..340445922d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -29,6 +29,26 @@ ENTRY(lowlevel_init)
ldr x0, =CCI_AUX_CONTROL_BASE(20)
ldr x1, =0x00000010
bl ccn504_set_aux
+
+ /*
+ * Set forced-order mode in RNI-6, RNI-20
+ * This is required for performance optimization on LS2088A
+ * LS2080A family does not support setting forced-order mode,
+ * so skip this operation for LS2080A family
+ */
+ bl get_svr
+ lsr w0, w0, #16
+ ldr w1, =SVR_DEV_LS2080A
+ cmp w0, w1
+ b.eq 1f
+
+ ldr x0, =CCI_AUX_CONTROL_BASE(6)
+ ldr x1, =0x00000020
+ bl ccn504_set_aux
+ ldr x0, =CCI_AUX_CONTROL_BASE(20)
+ ldr x1, =0x00000020
+ bl ccn504_set_aux
+1:
#endif
/* Add fully-coherent masters to DVM domain */