summaryrefslogtreecommitdiff
path: root/arch/arm/cpu/tegra-common/cache.c
diff options
context:
space:
mode:
authorMasahiro Yamada <yamada.m@jp.panasonic.com>2015-02-20 17:04:04 +0900
committerTom Rini <trini@ti.com>2015-02-21 08:23:51 -0500
commit09f455dca74973ef5e42311162c8dff7e83d44a2 (patch)
tree3107041e5a3c55644d8323b121026b062884d079 /arch/arm/cpu/tegra-common/cache.c
parent620118403e1521b4c883848a84d2fb68e3fa1aa0 (diff)
ARM: tegra: collect SoC sources into mach-tegra
This commit moves files as follows: arch/arm/cpu/arm720t/tegra20/* -> arch/arm/mach-tegra/tegra20/* arch/arm/cpu/arm720t/tegra30/* -> arch/arm/mach-tegra/tegra30/* arch/arm/cpu/arm720t/tegra114/* -> arch/arm/mach-tegra/tegra114/* arch/arm/cpu/arm720t/tegra124* -> arch/arm/mach-tegra/tegra124/* arch/arm/cpu/arm720t/tegra-common/* -> arch/arm/mach-tegra/* arch/arm/cpu/armv7/tegra20/* -> arch/arm/mach-tegra/tegra20/* arch/arm/cpu/armv7/tegra30/* -> arch/arm/mach-tegra/tegra30/* arch/arm/cpu/armv7/tegra114/* -> arch/arm/mach-tegra/tegra114/* arch/arm/cpu/armv7/tegra124/* -> arch/arm/mach-tegra/tegra124/* arch/arm/cpu/armv7/tegra-common/* -> arch/arm/mach-tegra/* arch/arm/cpu/tegra20-common/* -> arch/arm/mach-tegra/tegra20/* arch/arm/cpu/tegra30-common/* -> arch/arm/mach-tegra/tegra30/* arch/arm/cpu/tegra114-common/* -> arch/arm/mach-tegra/tegra114/* arch/arm/cpu/tegra124-common/* -> arch/arm/mach-tegra/tegra124/* arch/arm/cpu/tegra-common/* -> arch/arm/mach-tegra/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Simon Glass <sjg@chromium.org> [ on nyan-big ] Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/cpu/tegra-common/cache.c')
-rw-r--r--arch/arm/cpu/tegra-common/cache.c46
1 files changed, 0 insertions, 46 deletions
diff --git a/arch/arm/cpu/tegra-common/cache.c b/arch/arm/cpu/tegra-common/cache.c
deleted file mode 100644
index 94f5bce90e..0000000000
--- a/arch/arm/cpu/tegra-common/cache.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Tegra cache routines */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch-tegra/ap.h>
-#include <asm/arch/gp_padctrl.h>
-
-void config_cache(void)
-{
- u32 reg = 0;
-
- /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
- asm volatile(
- "mrc p15, 0, r0, c1, c0, 1\n"
- "orr r0, r0, #0x41\n"
- "mcr p15, 0, r0, c1, c0, 1\n");
-
- /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
- if (tegra_get_chip() < CHIPID_TEGRA114)
- return;
-
- /*
- * Systems with an architectural L2 cache must not use the PL310.
- * Config L2CTLR here for a data RAM latency of 3 cycles.
- */
- asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
- reg &= ~7;
- reg |= 2;
- asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
-}