diff options
| author | Ashish kumar <Ashish.kumar@nxp.com> | 2016-01-27 18:09:32 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-02-01 13:58:22 -0800 |
| commit | 2ea3a448ccfdd3d6f7e01060ba8fa49bd97a73e0 (patch) | |
| tree | a65ac9fd65e9e8eda89f146b7bd4ece4a992b40e /arch/arm/cpu | |
| parent | 73a5de4c6ea5f0269013897654c7ff50da97323b (diff) | |
armv8: ls2080a: Implement workaround for core errata 829520, 833471
829520: Code bounded by indirect conditional branch might corrupt
instruction stream.
Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect
Predictor.
833471: VMSR FPSCR functional failure or deadlock.
Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv8/start.S | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 2ee60d60f1..67b166c7fd 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -168,6 +168,25 @@ apply_a57_core_errata: msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ #endif +#ifdef CONFIG_ARM_ERRATA_833471 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* FPSCR write flush. + * Note that in some cases where a flush is unnecessary this + could impact performance. */ + orr x0, x0, #1 << 38 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + +#ifdef CONFIG_ARM_ERRATA_829520 + mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ + /* Disable Indirect Predictor bit will prevent this erratum + from occurring + * Note that in some cases where a flush is unnecessary this + could impact performance. */ + orr x0, x0, #1 << 4 + msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ +#endif + #ifdef CONFIG_ARM_ERRATA_833069 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ /* Disable Enable Invalidates of BTB bit */ |