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authorFabio Estevam <fabio.estevam@freescale.com>2014-01-03 15:55:57 -0200
committerStefano Babic <sbabic@denx.de>2014-01-15 10:33:25 +0100
commit5f98d0b5d3038cb3345712bc779efacaba4322f7 (patch)
tree1cd9ea54fab25fa4f89de932d21fc87b2c0bc50a /arch/arm/cpu
parenta6bbee66197759f790de83181924bf1d2cf482b2 (diff)
mx6: clock: Pass the frequency as argument of enable_fec_anatop_clock()
Provide an argument to enable_fec_anatop_clock() to specify the clock frequency that will be generated. No changes are made to mx6slevk, which uses the default 50MHz fec clock. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index f12bba2944..5617a410da 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -323,7 +323,7 @@ static u32 get_mmdc_ch0_clk(void)
#endif
#ifdef CONFIG_FEC_MXC
-int enable_fec_anatop_clock(void)
+int enable_fec_anatop_clock(enum enet_freq freq)
{
u32 reg = 0;
s32 timeout = 100000;
@@ -331,7 +331,13 @@ int enable_fec_anatop_clock(void)
struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+ if (freq < ENET_25MHz || freq > ENET_125MHz)
+ return -EINVAL;
+
reg = readl(&anatop->pll_enet);
+ reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
+ reg |= freq;
+
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
(!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;