diff options
| author | Paul Kocialkowski <contact@paulk.fr> | 2016-02-27 19:19:02 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-03-15 15:12:50 -0400 |
| commit | 6e495a453f2d59aa1ca92d1177957bfe5012bec0 (patch) | |
| tree | 810e855edefa72dfec401862904144f3ad1763cd /arch/arm/cpu | |
| parent | 5e56b0a80e0763fbc0f4bd14a622bcff973d7f00 (diff) | |
omap4: Properly enable USB PHY clocks
This correctly enables the USB PHY clocks, by enabling CM_ALWON_USBPHY_CLKCTRL
and correctly setting CM_L3INIT_USBPHY_CLKCTRL's value.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/hw_data.c | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap4/prcm-regs.c | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 1cc20728ee..02c06c1577 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -380,6 +380,10 @@ void enable_basic_clocks(void) setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl, USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); + /* Enable 32 KHz clock for USB PHY */ + setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + do_enable_clocks(clk_domains_essential, clk_modules_hw_auto_essential, clk_modules_explicit_en_essential, diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c index a09581e55b..2f0e1e851a 100644 --- a/arch/arm/cpu/armv7/omap4/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c @@ -129,6 +129,7 @@ struct prcm_regs const omap4_prcm = { .cm_div_m2_dpll_unipro = 0x4a0081d0, .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, /* cm2.core */ .cm_l3_1_clkstctrl = 0x4a008700, |