diff options
author | Hans de Goede <hdegoede@redhat.com> | 2014-11-15 23:18:18 +0100 |
---|---|---|
committer | Hans de Goede <hdegoede@redhat.com> | 2015-01-14 14:56:36 +0100 |
commit | 7582e39eb0139e79c0f80d9d1862d3baa74dddcf (patch) | |
tree | 2cf2919c04977bb3e4ede27242d5682f19a99987 /arch/arm/cpu | |
parent | 10191ed098a0a1417d80148372784956220e8dca (diff) |
sun6i: dram: Do not try to initialize a second dram chan on A31s
The A31s only has one dram channel, so do not bother with trying to initialize
a second channel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/armv7/sunxi/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv7/sunxi/dram_sun6i.c | 20 |
2 files changed, 15 insertions, 7 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 3b6ae47329..1337b60ac5 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -10,6 +10,7 @@ obj-y += timer.o obj-y += board.o obj-y += clock.o +obj-y += cpu_info.o obj-y += pinmux.o obj-$(CONFIG_MACH_SUN6I) += prcm.o obj-$(CONFIG_MACH_SUN8I) += prcm.o @@ -21,7 +22,6 @@ obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o ifndef CONFIG_SPL_BUILD -obj-y += cpu_info.o ifdef CONFIG_ARMV7_PSCI obj-y += psci.o endif diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c index 8f567c6452..61bb8d4adf 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c @@ -369,18 +369,26 @@ unsigned long sunxi_dram_init(void) .rows = 16, }; + /* A31s only has one channel */ + if (sunxi_get_ss_bonding_id() == SUNXI_SS_BOND_ID_A31S) + para.chan = 1; + mctl_sys_init(); mctl_dll_init(0, ¶); - mctl_dll_init(1, ¶); + setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN); + + if (para.chan == 2) { + mctl_dll_init(1, ¶); + setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); + } - setbits_le32(&mctl_com->ccr, - MCTL_CCR_MASTER_CLK_EN | - MCTL_CCR_CH0_CLK_EN | - MCTL_CCR_CH1_CLK_EN); + setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN); mctl_channel_init(0, ¶); - mctl_channel_init(1, ¶); + if (para.chan == 2) + mctl_channel_init(1, ¶); + mctl_com_init(¶); mctl_port_cfg(); |